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IDT72420L10TP PDF预览

IDT72420L10TP

更新时间： 2024-11-11 20:18:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片光电二极管内存集成电路
页数 文件大小 规格书
11页 121K
描述
FIFO, 64X8, 6.5ns, Synchronous, CMOS, PDIP28, 0.300 INCH, THIN, PLASTIC, DIP-28

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IDT72420L10TP 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：0.300 INCH, THIN, PLASTIC, DIP-28针数：28
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.9
Is Samacsys：N最长访问时间：6.5 ns
最大时钟频率 (fCLK)：100 MHz周期时间：10 ns
JESD-30 代码：R-PDIP-T28JESD-609代码：e0
长度：34.671 mm内存密度：512 bit
内存集成电路类型：OTHER FIFO内存宽度：8
功能数量：1端子数量：28
字数：64 words字数代码：64
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64X8
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP28,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：5 V认证状态：Not Qualified
座面最大高度：4.572 mm最大待机电流：0.005 A
子类别：FIFOs最大压摆率：0.04 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.62 mm
Base Number Matches：1

IDT72420L10TP 数据手册

 浏览型号IDT72420L10TP的Datasheet PDF文件第2页浏览型号IDT72420L10TP的Datasheet PDF文件第3页浏览型号IDT72420L10TP的Datasheet PDF文件第4页浏览型号IDT72420L10TP的Datasheet PDF文件第5页浏览型号IDT72420L10TP的Datasheet PDF文件第6页浏览型号IDT72420L10TP的Datasheet PDF文件第7页 
IDT72420  
IDT72200  
IDT72210  
IDT72220  
IDT72230  
IDT72240  
CMOS SyncFIFO™  
64 x 8, 256 x 8,  
512 x 8, 1,024 x 8,  
2,048 x 8 and 4,096 x 8  
FEATURES:  
DESCRIPTION:  
• 64 x 8-bit organization (IDT72420)  
• 256 x 8-bit organization (IDT72200)  
• 512 x 8-bit organization (IDT72210)  
TheIDT72420/72200/72210/72220/72230/72240SyncFIFO™arevery  
high-speed, low-power First-In, First-Out (FIFO) memories with clocked  
read and write controls. These devices have a 64, 256, 512, 1,024, 2,048,  
and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable  
for a wide variety of data buffering needs, such as graphics, Local Area  
Networks (LANs), and interprocessor communication.  
These FIFOs have 8-bit input and output ports. The input port is  
controlled by a free-running clock (WCLK), and a Write Enable pin (WEN).  
Data is written into the Synchronous FIFO on every clock when WEN is  
asserted. The output port is controlled by another clock pin (RCLK) and a  
Read Enable pin (REN). The Read Clock can be tied to the Write Clock for  
single clock operation or the two clocks can run asynchronous of one  
another for dual clock operation. An Output Enable pin (OE) is provided on  
the read port for three-state control of the output.  
• 1,024 x 8-bit organization (IDT72220)  
• 2,048 x 8-bit organization (IDT72230)  
• 4,096 x 8-bit organization (IDT72240)  
• 10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/  
72240)  
• Read and Write Clocks can be asynchronous or coincidental  
• Dual-Ported zero fall-through time architecture  
• Empty and Full flags signal FIFO status  
• Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,  
respectively  
• Output enable puts output data bus in high-impedance state  
• Produced with advanced submicron CMOS technology  
• Available in 28-pin 300 mil plastic DIP  
• For surface mount product please see the IDT72421/72201/72211/ provided for improved system control. The partial (AE) flags are set to  
72221/72231/72241 data sheet  
These Synchronous FIFOs have twoendpointflags, Empty(EF)andFull  
(FF). Two partial flags, Almost-Empty (AE) and Almost-Full (AF), are  
Empty+7 and Full-7 for AE and AF respectively.  
These FIFOs are fabricated using IDT’s high-speed submicron CMOS  
technology.  
• Industrial temperature range (–40°C to +85°C) is available  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D7  
WCLK  
WEN  
INPUT REGISTER  
EF  
AE  
AF  
FF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
64 x 8, 256 x 8,  
512 x 8, 1,024 x 8,  
2,048 x 8, 4,096 x 8  
WRITE POINTER  
READ POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
RS  
REN  
OE  
2680 drw01  
Q0 - Q7  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
SEPTEMBER 2002  
1
2002 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice.  
DSC-2680/2  
1234567...11

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与IDT72420L10TP相关器件

型号 品牌 获取价格 描述 数据表
IDT72420L10TPG IDT

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 		CMOS SyncFIFO
IDT72420L10TPSCDS-W ETC

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 		x8 Synchronous FIFO
IDT72420L12TC IDT

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 		CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
IDT72420L12TCB IDT

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 		CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
IDT72420L12TP IDT

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 		CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
IDT72420L12TPB IDT

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 		CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
IDT72420L12TPSCDS-W ETC

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 		x8 Synchronous FIFO
IDT72420L15SCDS-W IDT

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 		FIFO, 64X8, 10ns, Synchronous, CMOS, DIE
IDT72420L15TC IDT

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 		CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
IDT72420L15TCB IDT

获取价格

 		CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

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