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IDT723672 PDF预览

IDT723672

更新时间: 2024-11-11 04:58:27
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
29页 258K
描述
CMOS SyncBiFIFO

IDT723672 数据手册

 浏览型号IDT723672的Datasheet PDF文件第2页浏览型号IDT723672的Datasheet PDF文件第3页浏览型号IDT723672的Datasheet PDF文件第4页浏览型号IDT723672的Datasheet PDF文件第5页浏览型号IDT723672的Datasheet PDF文件第6页浏览型号IDT723672的Datasheet PDF文件第7页 
CMOS SyncBiFIFOTM  
2,048 x 36 x 2  
4,096 x 36 x 2  
IDT723652  
IDT723662  
IDT723672  
8,192 x 36 x 2  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving  
120-pin Thin Quad Flatpack (TQFP)  
Pincompatibletothelowerdensityparts,IDT723622/723632/723642  
Industrial temperature range (–40°C to +85°C) is available  
FEATURES  
Memory storage capacity:  
IDT723652  
IDT723662  
IDT723672  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
Supports clock frequencies up to 83MHz  
Fast access times of 8ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
DESCRIPTION  
TheIDT723652/723662/723672isamonolithic,high-speed,low-power,  
Two independent clocked FIFOs buffering data in opposite direc- CMOS Bidirectional SyncFIFO (clocked) memories which support clock  
tions  
frequencies up to 83MHz and have read access times as fast as 8ns. Two  
independent2,048/4,096/8,192x36dual-portSRAMFIFOs onboardeach  
chipbufferdatainoppositedirections. Communicationbetweeneachportmay  
bypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailboxregisterhas  
a flag to signal when new mail has been stored.  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
MBA  
Port-A  
Control  
Logic  
RAM  
ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
13  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
Port-B  
Control  
Logic  
Mail 2  
Register  
5609 drw 01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
NOVEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5609/4  

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