Datasheet > IDT723674

IDT723674

更新时间： 2024-11-11 04:58:27

品牌	Logo	应用领域
艾迪悌 - IDT		配套器件先进先出芯片
页数	文件大小	规格书
37页	396K
描述
CMOS SyncBiFIFO WITH BUS-MATCHING

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中文翻译

获取价格

数据手册

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IDT723674 数据手册

CMOS SyncBiFIFO^TMWITH BUS-MATCHING

2,048 x 36 x 2

4,096 x 36 x 2

IDT723654

IDT723664

IDT723674

8,192 x 36 x 2

• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

• Big- or Little-Endian format for word and byte bus sizes

• Retransmit Capability

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

• Mailbox bypass registers for each FIFO

• Free-running CLKA and CLKB may be asynchronous or coincident

(simultaneous reading and writing of data on a single clock edge

is permitted)

• Auto power down minimizes power dissipation

• Available in space saving 128-pin Thin Quad Flatpack (TQFP)

• Pincompatibletothelowerdensityparts, IDT723624/723634/723644

• Industrial temperature range (–40°C to +85°C) is available

FEATURES

• Memory storage capacity:

IDT723654

IDT723664

IDT723674

–

2,048 x 36 x 2

4,096 x 36 x 2

8,192 x 36 x 2

• Clock frequencies up to 83 MHz (8ns access time)

• Two independent clocked FIFOs buffering data in opposite

directions

• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRB flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has five

default offsets (8, 16, 64, 256 and 1,024 )

• Serial or parallel programming of partial flags

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

Port-A

Control

Logic

CSA

W/RA

ENA

RAM ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

MBA

FIFO1,

Mail1

Reset

Logic

MRS1

PRS1

Write

Pointer

Read

Pointer

Status Flag

Logic

EFB/ORB

AEB

FFA/IRA

AFA

FIFO1

FIFO2

FS2

FS0/SD

Programmable Flag

Offset Registers

Timing

Mode

FWFT

FS1/SEN

B0-B35

A0-A35

Status Flag

Logic

EFA/ORA

FFB/IRB

AFB

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RT1

RTM

RT2

FIFO1 and

FIFO2

Retransmit

Logic

RAM ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

Mail 2

SIZE

MBF2

5608 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

NOVEMBER 2003

COMMERCIAL TEMPERATURE RANGE



DSC-5608/5

12 3 4 5 6 7...37

中文翻译

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与IDT723674相关器件

型号	品牌	获取价格	描述	数据表
IDT723674L12PF	IDT	获取价格	CMOS SyncBiFIFO WITH BUS-MATCHING
IDT723674L12PF8	IDT	获取价格	Bi-Directional FIFO, 8KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT723674L12PF9	IDT	获取价格	FIFO, 8KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT723674L12PFG	IDT	获取价格	暂无描述
IDT723674L12PFG8	IDT	获取价格	FIFO, 8KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT723674L15PF	IDT	获取价格	CMOS SyncBiFIFO WITH BUS-MATCHING
IDT723674L15PFG	IDT	获取价格	暂无描述
IDT723674L15PFG8	IDT	获取价格	FIFO, 8KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT723674L20PF	IDT	获取价格	Bi-Directional FIFO, 8KX36, 12ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT723676	IDT	获取价格	CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

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