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IDT723611 PDF预览

IDT723611

更新时间: 2024-11-12 22:57:19
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
20页 240K
描述
CMOS SyncFIFO 64 x 36

IDT723611 数据手册

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IDT723611  
CMOS SyncFIFO  
64 x 36  
Integrated Device Technology, Inc.  
• Fast access times of 10ns  
FEATURES:  
• Available in 132-pin Plastic Quad Flatpack (PQF) or  
space-saving 120-pin Thin Quad Flatpack (PF)  
• Low-power advanced CMOS technology  
• Free-running CLKA and CLKB may be asynchronous or  
coincident (permits simultaneous reading and writing of  
data on a single clock edge)  
• Industrial temperature range (-40oC to +85oC) is avail-  
able, tested to military elecrical specifications  
• 64 x 36 storage capacity  
• Synchronous data buffering from Port A to Port B  
• Mailbox bypass register in each direction  
• Programmable Almost-Full (AF) and Almost-Empty (AE)  
flags  
• Microprocessor Interface Control Logic  
• Full Flag (FF) and Almost-Full (AF) flags synchronized by  
CLKA  
• Empty Flag (EF) and Almost-Empty (AE) flags synchro-  
nized by CLKB  
• Passive parity checking on each Port  
• Parity Generation can be selected for each Port  
• Supports clock frequencies up to 67MHz  
DESCRIPTION:  
The IDT723611 is a monolithic, high-speed, low-power,  
CMOS Synchronous (clocked) FIFO memory which supports  
clock frequencies up to 67MHz and has read access times as  
fastas10ns.The64x36dual-portFIFObuffersdatafromPort  
A to Port B. The FIFO has flags to indicate empty and full  
conditions,andtwoprogrammableflags,Almost-Full(AF)and  
Almost-Empty (AE), to indicate when a selected number of  
words is stored in memory. Communication between each  
port can take place through two 36-bit mailbox registers. Each  
FUNCTIONAL BLOCK DIAGRAM  
CLKA  
CSA  
W/RA  
ENA  
Port-A  
Control  
Logic  
MBA  
MBF1  
PEFB  
Parity  
Gen/Check  
Mail 1  
Register  
PGB  
RST  
Reset  
Logic  
ODD/  
EVEN  
64 x 36  
SRAM  
36  
36  
A0 - A35  
Read  
Pointer  
Write  
Pointer  
B0 - B35  
Status Flag  
FF  
AF  
EF  
AE  
Logic  
FIFO  
Programmable  
Flag Offset  
Registers  
FS0  
FS1  
PGA  
Mail 2  
Register  
Parity  
Gen/Check  
CLKB  
CSB  
Port-B  
Control  
Logic  
PEFA  
MBF2  
W/RB  
ENB  
MBB  
3024 drw 01  
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
MAY 1997  
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  
1997 Integrated Device Technology, Inc.  
DSC-3024/4  
1

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