CMOS SyncFIFOTM
64 x 36
IDT723611
FEATURES:
DESCRIPTION:
• Free-running CLKA and CLKB may be asynchronous or coincident
(permits simultaneous readingandwritingofdata ona single clock
edge)
TheIDT723611isamonolithic,high-speed,low-power,CMOSSynchro-
nous(clocked)FIFOmemorywhichsupportsclockfrequenciesupto67MHz
andhasreadaccesstimesasfastas10ns. The64x36dual-portFIFObuffers
datafromPortAtoPortB. TheFIFOhasflagstoindicateemptyandfullconditions,
and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to
indicatewhenaselectednumberofwordsisstoredinmemory. Communication
betweeneachportcantakeplacethroughtwo36-bitmailboxregisters. Each
mailboxregisterhas a flagtosignalwhen newmailhas beenstored. Parity
is checked passively on each port and may be ignored if not desired. Parity
generationcanbeselectedfordatareadfromeachport. Twoormoredevices
may be used in parallel to create wider data paths.
• 64 x 36 storage capacity
• Synchronous data buffering from Port A to Port B
• Mailbox bypass register in each direction
• Programmable Almost-Full (AF) and Almost-Empty (AE) flags
• Microprocessor Interface Control Logic
• Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
• Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
• Passive parity checking on each Port
The IDT723611 is a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface. Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
• Parity Generation can be selected for each Port
• Supports clock frequencies up to 67MHz
• Fast access times of 10ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
CLKA
Port-A
Control
Logic
CSA
W/RA
ENA
MBA
MBF1
PEFB
Parity
Mail 1
Register
Gen/Check
PGB
RST
Reset
Logic
ODD/
EVEN
RAM
ARRAY
64 x 36
36
A
0
- A35
Read
Pointer
Write
Pointer
B0 - B35
Status Flag
FF
AF
EF
AE
Logic
FIFO
Programmable
Flag Offset
Registers
FS
FS
0
1
Mail 2
Register
PGA
Parity
Gen/Check
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
PEFA
MBF2
3024 drw 01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
JUNE 2005
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3024/2