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IDT72285L15TFG8 PDF预览

IDT72285L15TFG8

更新时间: 2024-11-13 15:34:47
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 301K
描述
FIFO, 64KX18, 10ns, Synchronous, CMOS, PQFP64, STQFP-64

IDT72285L15TFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:STQFP-64针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.83
最长访问时间:10 ns其他特性:RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
周期时间:15 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:10 mm
内存密度:1179648 bit内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:64字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX18可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

IDT72285L15TFG8 数据手册

 浏览型号IDT72285L15TFG8的Datasheet PDF文件第2页浏览型号IDT72285L15TFG8的Datasheet PDF文件第3页浏览型号IDT72285L15TFG8的Datasheet PDF文件第4页浏览型号IDT72285L15TFG8的Datasheet PDF文件第5页浏览型号IDT72285L15TFG8的Datasheet PDF文件第6页浏览型号IDT72285L15TFG8的Datasheet PDF文件第7页 
CMOS SuperSync FIFO™  
32,768 x 18  
65,536 x 18  
IDT72275  
IDT72285  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-  
pin Slim Thin Quad Flat Pack (STQFP)  
High-performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
FEATURES:  
Choose among the following memory organizations:  
IDT72275 — 32,768 x 18  
IDT72285 — 65,536 x 18  
Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs  
10ns read/write cycle time (6.5ns access time)  
Fixed, low first word data latency time  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable  
settings  
Retransmit operation with fixed, low first word data  
latency time  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag  
can default to one of two preselected offsets  
Program partial flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First  
Word Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
DESCRIPTION:  
TheIDT72275/72285areexceptionallydeep,highspeed,CMOSFirst-In-  
First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs  
offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe  
following:  
Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas  
been removed. The Frequency Select pin (FS) has been removed, thus  
it is no longer necessary to select which of the two clock inputs, RCLK or  
WCLK, is runningatthe higherfrequency.  
The period required by the retransmit operation is now fixed and short.  
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan  
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable  
clock cycle counting delay associated with the latency period found on  
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)  
FUNCTIONAL BLOCK DIAGRAM  
D0 -D17  
WEN  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
FWFT/SI  
RAM ARRAY  
32,768 x 18  
65,536 x 18  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
4674 drw 01  
Q0 -Q17  
OE  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
FEBRUARY 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4674/4  

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