IDT72285L20TFI

更新时间： 2024-11-13 13:08:43

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
25页	227K
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数据手册

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IDT72285L20TFI 数据手册

CMOS SUPERSYNC FIFO™

32,768 x 18

PRELIMINARY

IDT72275

65,536 x 18

IDT72285

Integrated Device Technology, Inc.

• Independent Read and Write Clocks (permit reading and

writing simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the

64-pin Slim Thin Quad Flat Pack (STQFP)

FEATURES:

• Choose among the following memory organizations:

IDT72275

IDT72285

32,768 x 18

65,536 x 18

• High-performance submicron CMOS technology

• Pin-compatible with the IDT72255LA/72265LA SuperSync

FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

DESCRIPTION:

The IDT72275/72285 are exceptionally deep, high speed,

CMOS First-In-First-Out (FIFO) memories with clocked read

and write controls. These FIFOs offer numerous improve-

mentsoverpreviousSuperSyncFIFOs,includingthefollowing:

• The limitation of the frequency of one clock input with

respect to the other has been removed. The Frequency

Select pin (FS) has been removed, thus it is no longer

necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed

and short.

• The first word data latency period, from the time the first

word is written to an empty FIFO to the time it can be read,

is now fixed and short. (The variable clock cycle counting

•

Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

FUNCTIONAL BLOCK DIAGRAM

D0 -D17

WCLK

OFFSET REGISTER

INPUT REGISTER

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

32,768 x 18

65,536 x 18

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

RESET

LOGIC

RCLK

4674 drw 01

Q0 -Q17

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

SEPTEMBER 1998

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

DSC-4674/-

12 3 4 5 6 7...25

中文翻译

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与IDT72285L20TFI相关器件

型号	品牌	获取价格	描述	数据表
IDT72285L20TFI8	IDT	获取价格	FIFO, 64KX18, 12ns, Synchronous, CMOS, PQFP64, STQFP-64
IDT72285L20TFI9	IDT	获取价格	FIFO, 64KX18, 12ns, Synchronous, CMOS, PQFP64, STQFP-64
IDT72291	IDT	获取价格	CMOS SuperSync FIFO
IDT72291L	IDT	获取价格	CMOS SuperSync FIFO
IDT72291L10PF	IDT	获取价格	CMOS SuperSync FIFO
IDT72291L10PF9	IDT	获取价格	FIFO, 128KX9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72291L10PFG	IDT	获取价格	FIFO, 128KX9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72291L10PFG8	IDT	获取价格	FIFO, 128KX9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72291L10PFI	IDT	获取价格	CMOS SuperSync FIFO
IDT72291L10TF	IDT	获取价格	CMOS SuperSync FIFO

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