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IDT71V65903S85PFI8 PDF预览

IDT71V65903S85PFI8

更新时间： 2024-11-08 15:46:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 609K
描述
ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100

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IDT71V65903S85PFI8 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.33最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK)：90 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.06 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.06 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

IDT71V65903S85PFI8 数据手册

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256K x 36, 512K x 18  
IDT71V65703  
IDT71V65903  
3.3VSynchronousZBT™SRAMs  
3.3V I/O, Burst Counter  
Flow-Through Outputs  
Features  
Address and control signals are applied to the SRAM during one  
clock cycle, and on the next clock cycle the associated data cycle  
occurs, be it read or write.  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 100 MHz  
The IDT71V65703/5903 contain address, data-in and control  
signal registers. The outputs are flow-through (no output data  
register). Output enable is the only asynchronous signal and can be  
used to disable the outputs at any given time.  
(7.5 ns Clock-to-Data Access)  
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
◆
Internally synchronized output buffer enable eliminates the  
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen  
CEN is high and the internal device registers will hold their previous values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
user to deselect the device when desired. If any one of these three  
is not asserted when ADV/LD is low, no new memory operation can  
be initiated. However, any pending data transfers (reads or writes)  
will be completed. The data bus will tri-state one cycle after the chip  
is deselected or a write is initiated.  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
◆
◆
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
The IDT71V65703/5903 SRAMs utilize a high-performance CMOS  
process and are packaged in a JEDEC Standard 14mm x 20mm 100-  
pin plasticthinquadflatpack(TQFP), 119 ballgridarray(BGA) and a 165  
fine pitch ball grid array (fBGA).  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Green parts available, see ordering information  
◆
Description  
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit  
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.  
They are designed to eliminate dead bus cycles when turning the bus  
aroundbetweenreadsandwrites, orwritesandreads. Thustheyhave  
been given the name ZBTTM, or Zero Bus Turnaround.  
Pin Description Summary  
A
0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE  
2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
BW , BW  
CLK  
Individual Byte Write Selects  
Clock  
1
2, BW3, BW4  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O  
0
-I/O31 , I/OP1-I/OP4  
Data Input/Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5298 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2014  
1
©2014 Integrated Device Technology, Inc.  
DSC-5298/05  
1234567...23

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602133BQ IDT

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IDT71V67602133PF IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602133PFI IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602150BG IDT

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 		256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602150BGI IDT

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