5秒后页面跳转
IDT71V67602S133BQ PDF预览

IDT71V67602S133BQ

更新时间: 2024-11-10 05:22:51
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器时钟
页数 文件大小 规格书
22页 975K
描述
256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect

IDT71V67602S133BQ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:13 X 15 MM, FBGA-165
针数:165Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.81Is Samacsys:N
最长访问时间:4.2 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B165JESD-609代码:e0
长度:15 mm内存密度:9437184 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:165字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TBGA
封装等效代码:BGA165,11X15,40封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.07 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.28 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:13 mm
Base Number Matches:1

IDT71V67602S133BQ 数据手册

 浏览型号IDT71V67602S133BQ的Datasheet PDF文件第2页浏览型号IDT71V67602S133BQ的Datasheet PDF文件第3页浏览型号IDT71V67602S133BQ的Datasheet PDF文件第4页浏览型号IDT71V67602S133BQ的Datasheet PDF文件第5页浏览型号IDT71V67602S133BQ的Datasheet PDF文件第6页浏览型号IDT71V67602S133BQ的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
2.5V I/O, Burst Counter  
IDT71V67602  
IDT71V67802  
PipelinedOutputs,SingleCycleDeselect  
Features  
Description  
256K x 36, 512K x 18 memory configurations  
Supports high system speed:  
The IDT71V67602/7802 are high-speed SRAMs organized as  
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67602/7802canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
andthe LBO inputpin.  
TheIDT71V67602/7802SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1 )  
BW1, BW2, BW3, BW4  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
VDD, VDDQ  
VSS  
Supply  
Supply  
N/A  
5311 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V67802.  
DECEMBER 2003  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5311/07  

与IDT71V67602S133BQ相关器件

型号 品牌 获取价格 描述 数据表
IDT71V67602S133BQG IDT

获取价格

暂无描述
IDT71V67602S133BQGI IDT

获取价格

暂无描述
IDT71V67602S133BQI IDT

获取价格

256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602S133PF IDT

获取价格

256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602S133PF8 IDT

获取价格

Cache SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V67602S133PFG IDT

获取价格

Cache SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQF
IDT71V67602S133PFG8 IDT

获取价格

Cache SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQF
IDT71V67602S133PFGI IDT

获取价格

Cache SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, TQF
IDT71V67602S133PFI IDT

获取价格

256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin
IDT71V67602S150BG IDT

获取价格

256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Sin