IDT71V3577YS_79YS, IDT71V3577YSA_79YSA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
A
7
A
8
NC
CE
1
BW
3
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
(4)
NC
A6
CS
0
CLK
A9
NC
BW4
BW1
I/OP3
I/O17
I/O19
I/O21
I/O23
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
10
11
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/OP2
I/O14
I/O12
I/O10
I/O16
I/O18
I/O20
I/O22
NC
V
V
V
V
V
V
V
I/O15
I/O13
I/O11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
G
H
J
VDDQ
V
V
V
V
V
V
I/O
NC
I/O
I/O
I/O
I/O
NC
9
I/O8
(3)
V
SS(1)
NC
V
V
V
V
V
NC
ZZ
I/O
I/O
I/O
I/O
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
13
7
6
K
L
M
N
P
V
V
V
V
V
V
V
5
4
V
V
V
V
V
V
V
3
2
V
V
V
V
V
V
V
1
0
NC/TRST(2, 5)
(4)
V
V
NC
NC
V
V
I/OP1
(4)
(2)
(2)
(4)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A14
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
A0
NC/TCK
A
A12
A15
A16
LBO
6450 tbl 17
Pin Configuration – 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
7
NC
A
8
A10
CE
1
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
(4)
A6
CS
0
NC
CLK
A9
NC
BW1
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
11
12
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/OP1
I/O
8
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
7
I/O
9
V
V
V
V
V
V
V
6
I/O10
I/O11
NC
V
V
V
V
V
V
V
5
G
H
J
VDDQ
V
V
V
V
V
V
4
(3)
V
SS(1)
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
NC
V
V
V
V
V
NC
ZZ
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
14
13
I/O
I/O
I/O
3
NC
NC
NC
NC
NC
K
L
M
N
P
NC
V
V
V
V
V
V
V
2
NC
V
V
V
V
V
V
V
1
NC
V
V
V
V
V
V
V
I/O
0
(4)
NC
V
V
NC/TRST(2, 5)
NC
NC
V
V
NC
(4)
(2)
(2)
(4)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A15
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
A0
NC/TCK
A
A
A16
A17
LBO
6450 tbl 17a
NOTES:
1. H1 does not have to be directly VSS as long as input voltage is < VIL
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.482