IDT71V3579YSA80B

更新时间： 2024-01-29 00:51:28

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
22页	522K
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IDT71V3579YSA80B 数据手册

IDT71V3577S

IDT71V3579S

IDT71V3577SA

IDT71V3579SA

128K X 36, 256K X 18

3.3V Synchronous SRAMs

3.3V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Description

Features

◆

The IDT71V3577/79 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V3577/79SRAMs containwrite,data,

address andcontrolregisters.Therearenoregisters inthedataoutput

path(flow-througharchitecture).InternallogicallowstheSRAMtogen-

erateaself-timedwritebaseduponadecisionwhichcanbeleftuntilthe

endofthe write cycle.

128K x 36, 256K x 18 memory configurations

◆

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

CommercialandIndustrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V3577/79canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe

arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe

next three rising clock edges. The order of these three addresses are

definedbytheinternalburstcounterandtheLBO inputpin.

◆

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

◆

Packaged in a JEDEC Standard 100-pin plastic thin quad

The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball

grid array

PinDescriptionSummary

A⁰-A¹⁷

Address Inputs

Input

Synchronous

Asynchronous

Synchronous

Chip Enable

CS⁰, CS1

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

BWE

(1)

BW¹, BW², BW³, BW4

CLK

ADV

ADSC

ADSP

LBO

Clock

Input

Output

Input

I/O

N/A

Synchronous

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

TRST

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

N/A

NOTE:

5280 tbl 01

1. BW3 and BW4 are not applicable for the IDT71V3579.

FEBRUARY 2005

DSC-5280/08

12 3 4 5 6 7...22

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与IDT71V3579YSA80B相关器件

型号	品牌	描述	获取价格	数据表
IDT71V3579YSA80BGG	IDT	128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter,	获取价格
IDT71V3579YSA80BGGI	IDT	128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter,	获取价格
IDT71V3579YSA80BGGI8	IDT	Standard SRAM, 256KX18, 8ns, CMOS, PBGA119	获取价格
IDT71V3579YSA80BGI8	IDT	Standard SRAM, 256KX18, 8ns, CMOS, PBGA119	获取价格
IDT71V3579YSA80BQ	IDT	Cache SRAM, 256KX18, 8ns, CMOS, PBGA165, FBGA-165	获取价格
IDT71V3579YSA80BQ8	IDT	Standard SRAM, 256KX18, 8ns, CMOS, PBGA165	获取价格

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