IDT71V3559S75BGI

更新时间： 2024-11-13 22:26:19

品牌	Logo	应用领域
艾迪悌 - IDT		计数器存储内存集成电路静态存储器
页数	文件大小	规格书
28页	997K
描述
128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs

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技术参数
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IDT71V3559S75BGI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	BGA,	针数：	119
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.46
最长访问时间：	7.5 ns	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	119
字数：	262144 words	字数代码：	256000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	256KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified	座面最大高度：	2.36 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

IDT71V3559S75BGI 数据手册

128K x 36, 256K x 18,

IDT71V3557S

IDT71V3559S

IDT71V3557SA

IDT71V3559SA

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter,

Flow-Through Outputs

Features

it read or write.

◆

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

The IDT71V3557/59 contain address, data-in and control signal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted

when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will

be completed. The data bus will tri-state one cycle after chip is de-

selectedorawriteisinitiated.

The IDT71V3557/59 have an on-chip burst counter. In the burst

mode, the IDT71V3557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates

the need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW¹- BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)

Optional Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array (fBGA)

◆

Description

TheIDT71V3557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronous SRAMs organizedas 128Kx36/256Kx18. Theyare

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT^TM, or Zero Bus Turnaround.

The IDT71V3557/59 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thinplasticquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycletheassociateddatacycleoccurs,be

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE2, CE²

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW⁴

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

LBO

TMS

Synchronous

N/A

TDI

TCK

Te s t Cl o c k

TDO

Te s t Data Outp ut

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

I/O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

VSS

Static

52 82 tb l 01

OCTOBER 2004

DSC-5282/07

12 3 4 5 6 7...28

中文翻译

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与IDT71V3559S75BGI相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3559S75BQ	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S75BQG	IDT	获取价格	Synchronous ZBT SRAMs
IDT71V3559S75BQGI	IDT	获取价格	Synchronous ZBT SRAMs
IDT71V3559S75BQI	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S75PF	IDT	获取价格	128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S75PF8	IDT	获取价格	ZBT SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
IDT71V3559S75PF9	IDT	获取价格	ZBT SRAM, 256KX18, 7.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
IDT71V3559S75PFG	IDT	获取价格	Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLA
IDT71V3559S75PFG8	IDT	获取价格	Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLA
IDT71V3559S75PFGI	IDT	获取价格	Synchronous ZBT SRAMs

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