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IDT71V3559S75PFI8 PDF预览

IDT71V3559S75PFI8

更新时间： 2024-11-14 20:47:55
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 487K
描述
ZBT SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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IDT71V3559S75PFI8 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.58最长访问时间：7.5 ns
其他特性：FLOW-THROUGH ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

IDT71V3559S75PFI8 数据手册

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128K x 36, 256K x 18,  
IDT71V3557  
IDT71V3559  
3.3V Synchronous ZBT™ SRAMs  
3.3V I/O, Burst Counter,  
Flow-Through Outputs  
Features  
The IDT71V3557/59 contain address, data-in and control signal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V3557/59  
to be suspended as long as necessary. All synchronous inputs are  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted  
when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will  
be completed. The data bus will tri-state one cycle after chip is de-  
selectedorawriteisinitiated.  
The IDT71V3557/59 have an on-chip burst counter. In the burst  
mode, the IDT71V3557/59 can provide four cycles of data for a single  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
◆
128K x 36, 256K x 18 memory configurations  
◆
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
◆
cycles  
◆
Internally synchronized output buffer enable eliminates  
the need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V (±5%) I/O Supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
◆
◆
◆
◆
◆
◆
◆
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine  
pitch ball grid array (fBGA)  
Description  
TheIDT71V3557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit)synchronous SRAMs organizedas 128Kx36/256Kx18. Theyare  
designed to eliminate dead bus cycles when turning the bus around  
between reads and writes, or writes and reads. Thus they have been  
The IDT71V3557/59 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pin thinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
TM  
given the name ZBT , or Zero Bus Turnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be  
it read or write.  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Data Input / Output  
Core Power, I/O Power  
Ground  
Synchronous  
Static  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Synchronous  
Static  
DD DDQ  
V , V  
Supply  
Supply  
SS  
V
Static  
5282 tbl 01  
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.  
OCTOBER 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-5282/05  
1234567...26

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与IDT71V3559S75PFI8相关器件

型号 品牌 获取价格 描述 数据表
IDT71V3559S80BG IDT

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 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S80BG8 IDT

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 		ZBT SRAM, 256KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3559S80BGG IDT

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 		Synchronous ZBT SRAMs
IDT71V3559S80BGGI IDT

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 		Synchronous ZBT SRAMs
IDT71V3559S80BGI IDT

获取价格

 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S80BGI8 IDT

获取价格

 		ZBT SRAM, 256KX18, 8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3559S80BQ IDT

获取价格

 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out
IDT71V3559S80BQG IDT

获取价格

 		Cache SRAM, 256KX18, 8ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165
IDT71V3559S80BQGI IDT

获取价格

 		Cache SRAM, 256KX18, 8ns, CMOS, PBGA165, 13 X 15 MM, ROHS COMPLIANT, FBGA-165
IDT71V3559S80BQI IDT

获取价格

 		128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Out

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