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IDT71V3558S200PF9 PDF预览

IDT71V3558S200PF9

更新时间: 2024-11-14 20:06:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
28页 499K
描述
ZBT SRAM, 256KX18, 3.2ns, CMOS, PQFP100, PLASTIC, TQFP-100

IDT71V3558S200PF9 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.7
Is Samacsys:NBase Number Matches:1

IDT71V3558S200PF9 数据手册

 浏览型号IDT71V3558S200PF9的Datasheet PDF文件第2页浏览型号IDT71V3558S200PF9的Datasheet PDF文件第3页浏览型号IDT71V3558S200PF9的Datasheet PDF文件第4页浏览型号IDT71V3558S200PF9的Datasheet PDF文件第5页浏览型号IDT71V3558S200PF9的Datasheet PDF文件第6页浏览型号IDT71V3558S200PF9的Datasheet PDF文件第7页 
IDT71V3556S  
IDT71V3558S  
IDT71V3556SA  
IDT71V3558SA  
128K x 36, 256K x 18  
3.3VSynchronousZBTSRAMs  
3.3V I/O, Burst Counter  
PipelinedOutputs  
Description  
Features  
TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit) synchronous SRAMS. They are designed to eliminate dead bus  
cycles when turning the bus around between reads and writes, or  
writes and reads. Thus, they have been given the name ZBTTM, or  
Zero Bus Turnaround.  
128K x 36, 256K x 18 memory configurations  
Supports high performance system speed - 200 MHz  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Address and control signals are applied to the SRAM during one  
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit  
read or write.  
The IDT71V3556/58 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58  
to be suspended as long as necessary. All synchronous inputs are  
ignored when (CEN) is high and the internal device registers will hold  
their previous values.  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)  
Optional- Boundary Scan JTAG Interface (IEEE 1149.1  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
asserted when ADV/LD is low, no new memory operation can be  
initiated. However, anypendingdata transfers (reads orwrites)willbe  
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected  
orawriteisinitiated.  
compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW1, BW2, BW3, BW4  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
5281 tbl 01  
JANUARY 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5281/07  

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