Datasheet > IDT71V3558SA

IDT71V3558SA

更新时间： 2024-11-13 23:08:19

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
28页	1011K
描述
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

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IDT71V3558SA 数据手册

IDT71V3556S

IDT71V3558S

IDT71V3556SA

IDT71V3558SA

128K x 36, 256K x 18

3.3VSynchronousZBTSRAMs

3.3V I/O, Burst Counter

PipelinedOutputs

Description

Features

◆

TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT^TM, or

Zero Bus Turnaround.

128K x 36, 256K x 18 memory configurations

◆

Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

cycles

◆

Address and control signals are applied to the SRAM during one

clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit

read or write.

The IDT71V3556/58 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V3556/58

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

Internally synchronized output buffer enable eliminates the

need to control OE

◆

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)

Optional- Boundary Scan JTAG Interface (IEEE 1149.1

◆

Therearethreechipenablepins(CE¹,CE2,CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be

initiated. However, anypendingdata transfers (reads orwrites)willbe

completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected

orawriteisinitiated.

compliant)

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

PinDescriptionSummary

A⁰-A¹⁷

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE², CE2

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW4

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

Static

5281 tbl 01

SEPTEMBER 2004

DSC-5281/08

12 3 4 5 6 7...28

中文翻译

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与IDT71V3558SA相关器件

型号	品牌	获取价格	描述	数据表
IDT71V3558SA100BG	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
IDT71V3558SA100BG8	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, POWER, PLASTIC, BGA-119
IDT71V3558SA100BGG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3558SA100BGG8	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119
IDT71V3558SA100BGGI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3558SA100BGGI8	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119
IDT71V3558SA100BQG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3558SA100BQGI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs
IDT71V3558SA100BQI8	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA165
IDT71V3558SA100PFG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

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