Datasheet > 存储 > SRAM> IDT71V30L25TFI

IDT71V30L25TFI

更新时间： 2024-11-03 22:10:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	121K
描述
HIGH-SPEED 3.3V 1K X 8 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT71V30L25TFI 数据手册

IDT71V30S/L

HIGH-SPEED 3.3V

1K X 8 DUAL-PORT

STATIC RAM

Features

◆

High-speed access

On-chip port arbitration logic

◆

Interrupt flags for port-to-port communication

– Commercial: 25/35/55ns (max.)

Low-power operation

– IDT71V30S

— Active: 375mW (typ.)

— Standby: 5mW (typ.)

– IDT71V30L

◆

Fully asynchronous operation from either port

Battery backup operation, 2V data retention (L Only)

TTL-compatible, single 3.3V ±0.3V power supply

Industrial temperature range (-40^OC to +85^OC) is available

for selected speeds

— Active: 375mW (typ.)

— Standby: 1mW (typ.)

Functional Block Diagram

OER

OEL

CER

R/WR

CEL

R/WL

I/O0R-I/O7R

I/O0L- I/O7L

I/O

Control

I/O

Control

(1)

BUSYL

(1)

BUSYR

A9L

A9R

Address

MEMORY

ARRAY

Address

Decoder

A0L

A0R

ARBITRATION

and

INTERRUPT

LOGIC

CE_L

OEL

CE_R

OER

R/WR

R/WL

(2)

INTL

(2)

INTR

3741 drw 01

NOTES:

1. IDT71V30: BUSY outputs are non-tristatable push-pulls.

2. INT outputs are non-tristable push-pull output structure.

JANUARY 2001

DSC 3741/7

12 3 4 5 6 7...14

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