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IDT71V25761S200BG8 PDF预览

IDT71V25761S200BG8

更新时间: 2024-09-28 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
21页 322K
描述
Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71V25761S200BG8 技术参数

是否Rohs认证:不符合生命周期:Not Recommended
零件包装代码:BGA包装说明:BGA, BGA119,7X17,50
针数:119Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.37Is Samacsys:N
最长访问时间:3.1 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:119字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:2.36 mm
最大待机电流:0.03 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.36 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

IDT71V25761S200BG8 数据手册

 浏览型号IDT71V25761S200BG8的Datasheet PDF文件第2页浏览型号IDT71V25761S200BG8的Datasheet PDF文件第3页浏览型号IDT71V25761S200BG8的Datasheet PDF文件第4页浏览型号IDT71V25761S200BG8的Datasheet PDF文件第5页浏览型号IDT71V25761S200BG8的Datasheet PDF文件第6页浏览型号IDT71V25761S200BG8的Datasheet PDF文件第7页 
128K X 36  
IDT71V25761YS/S  
3.3VSynchronousSRAMs  
2.5V I/O, Pipelined Outputs,  
Burst Counter, Single Cycle Deselect  
Features  
Description  
128K x 36 memory configuration  
TheIDT71V25761arehigh-speedSRAMsorganizedas128Kx36.  
The IDT71V25761 SRAMs contain write, data, address and control  
registers. InternallogicallowstheSRAMtogenerateaself-timedwrite  
basedupona decisionwhichcanbe leftuntilthe endofthe write cycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V25761canprovidefourcyclesofdatafor  
a single address presented to the SRAM. An internal burst address  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
Supports high system speed:  
Commercial:  
– 200MHz 3.1ns clock access time  
CommercialandIndustrial:  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
Compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball 100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
andthe LBO inputpin.  
The IDT71V25761 SRAMs utilize IDT’s latest high-performance  
grid array  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0
, CS  
1
Chip Selects  
Output Enable  
OE  
GW  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW  
(1)  
1
2
, BW  
3
, BW  
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
TMS  
TDI  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
5297 tbl 01  
MAY 2010  
1
©2010IntegratedDeviceTechnology,Inc.  
DSC-5297/05  

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