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IDT71V25761YS166BGI PDF预览

IDT71V25761YS166BGI

更新时间: 2024-01-03 16:26:21
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
22页 276K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119

IDT71V25761YS166BGI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.49
最长访问时间:3.5 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):166 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.03 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.32 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT71V25761YS166BGI 数据手册

 浏览型号IDT71V25761YS166BGI的Datasheet PDF文件第2页浏览型号IDT71V25761YS166BGI的Datasheet PDF文件第3页浏览型号IDT71V25761YS166BGI的Datasheet PDF文件第4页浏览型号IDT71V25761YS166BGI的Datasheet PDF文件第5页浏览型号IDT71V25761YS166BGI的Datasheet PDF文件第6页浏览型号IDT71V25761YS166BGI的Datasheet PDF文件第7页 
128K X 36, 256K X 18  
IDT71V25761S  
IDT71V25781S  
IDT71V25761SA  
IDT71V25781SA  
3.3VSynchronousSRAMs  
2.5V I/O, Pipelined Outputs,  
Burst Counter, Single Cycle Deselect  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
TheIDT71V25761/781arehigh-speedSRAMs organizedas 128K  
x 36/256K x 18. The IDT71V25761/781 SRAMs contain write, data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
Supports high system speed:  
Commercial:  
– 200MHz 3.1ns clock access time  
CommercialandIndustrial:  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V25761/718canprovidefourcyclesofdata  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
Compliant)  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
andthe LBO inputpin.  
TheIDT71V25761/781SRAMsutilizeIDT’slatesthigh-performance  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
grid array  
100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
TMS  
Synchronous  
Synchronous  
N/A  
TDI  
TCK  
Test Clock  
TDO  
Test Data Output  
Synchronous  
Asynchronous  
Asynchronous  
Synchronous  
N/A  
JTAG Reset (Optional)  
Sleep Mode  
TRST  
ZZ  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
N/A  
5297 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V25781.  
JUNE 2003  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-5297/03  

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IDT71V25761YS166BQI IDT

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Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA165, FBGA-165
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Cache SRAM, 128KX36, 3.3ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
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IDT71V25761YS200BQ IDT

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IDT71V25761YSA166BG IDT

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Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119
IDT71V25761YSA166BG8 IDT

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Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119
IDT71V25761YSA166BGI IDT

获取价格

Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119