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IDT71V25761YSA166BG PDF预览

IDT71V25761YSA166BG

更新时间: 2024-02-04 03:10:38
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 510K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119

IDT71V25761YSA166BG 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA-119
针数:119Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.52Is Samacsys:N
最长访问时间:3.5 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):166 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:119字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5,3.3 V
认证状态:Not Qualified座面最大高度:2.36 mm
最大待机电流:0.03 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.32 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

IDT71V25761YSA166BG 数据手册

 浏览型号IDT71V25761YSA166BG的Datasheet PDF文件第2页浏览型号IDT71V25761YSA166BG的Datasheet PDF文件第3页浏览型号IDT71V25761YSA166BG的Datasheet PDF文件第4页浏览型号IDT71V25761YSA166BG的Datasheet PDF文件第5页浏览型号IDT71V25761YSA166BG的Datasheet PDF文件第6页浏览型号IDT71V25761YSA166BG的Datasheet PDF文件第7页 
128K X 36, 256K X 18  
IDT71V25761  
IDT71V25781  
3.3VSynchronousSRAMs  
2.5V I/O, Pipelined Outputs,  
Burst Counter, Single Cycle Deselect  
Features  
Description  
128K x 36, 256K x 18 memory configurations  
TheIDT71V25761/781arehigh-speedSRAMs organizedas 128K  
x 36/256K x 18. The IDT71V25761/781 SRAMs contain write, data,  
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate  
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof  
thewritecycle.  
Supports high system speed:  
Commercial:  
– 200MHz 3.1ns clock access time  
CommercialandIndustrial:  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
LBO input selects interleaved or linear burst mode  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V25761/718canprovidefourcyclesofdata  
forasingleaddress presentedtotheSRAM. Aninternalburstaddress  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.  
grid array  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
TheIDT71V25761/781SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
0
1
CS , CS  
Chip Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1)  
1,  
2,  
3,  
4
BW BW BW BW  
CLK  
ADV  
ADSC  
ADSP  
LBO  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ZZ  
Asynchronous  
Synchronous  
N/A  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V , V  
Supply  
Supply  
SS  
V
N/A  
5297 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V25781.  
OCTOBER 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-5297/01  

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