128K X 36, 256K X 18
IDT71V25761
IDT71V25781
3.3VSynchronousSRAMs
2.5V I/O, Pipelined Outputs,
Burst Counter, Single Cycle Deselect
Features
Description
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128K x 36, 256K x 18 memory configurations
TheIDT71V25761/781arehigh-speedSRAMs organizedas 128K
x 36/256K x 18. The IDT71V25761/781 SRAMs contain write, data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof
thewritecycle.
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Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
CommercialandIndustrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V25761/718canprovidefourcyclesofdata
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
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Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O
Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.
grid array
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
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TheIDT71V25761/781SRAMsutilizeIDT’slatesthigh-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray
(BGA) and 165 fine pitch ball grid array (fBGA).
PinDescriptionSummary
0
17
A -A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
0
1
CS , CS
Chip Selects
Output Enable
OE
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
GW
BWE
(1)
1,
2,
3,
4
BW BW BW BW
CLK
ADV
ADSC
ADSP
LBO
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ZZ
Asynchronous
Synchronous
N/A
0
31
P1
P4
I/O -I/O , I/O -I/O
Data Input / Output
Core Power, I/O Power
Ground
DD DDQ
V , V
Supply
Supply
SS
V
N/A
5297 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V25781.
OCTOBER 2000
1
©2000IntegratedDeviceTechnology,Inc.
DSC-5297/01