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IDT71V2576183BG PDF预览

IDT71V2576183BG

更新时间: 2024-01-19 15:17:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
17页 294K
描述
Standard SRAM, 128KX36, 3.3ns, CMOS, PBGA119, BGA-119

IDT71V2576183BG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA,
针数:119Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.84Base Number Matches:1

IDT71V2576183BG 数据手册

 浏览型号IDT71V2576183BG的Datasheet PDF文件第2页浏览型号IDT71V2576183BG的Datasheet PDF文件第3页浏览型号IDT71V2576183BG的Datasheet PDF文件第4页浏览型号IDT71V2576183BG的Datasheet PDF文件第5页浏览型号IDT71V2576183BG的Datasheet PDF文件第6页浏览型号IDT71V2576183BG的Datasheet PDF文件第7页 
128K X 36, 256K X 18, 3.3V  
SYNCHRONOUS SRAMS WITH  
2.5V I/O OPTION, PIPELINED OUTPUTS,  
BURST COUNTER,  
PRELIMINARY  
IDT71V2576  
IDT71V2578  
IDT71V3576  
IDT71V3578  
SINGLE CYCLE DESELECT  
DESCRIPTION:  
FEATURES:  
The IDT71Vx576/578 are high-speed SRAMs organized as 128K x 36/  
256K x 18. The IDT71Vx576/578 SRAMs contain write, data, address and  
controlregisters. InternallogicallowstheSRAMtogenerateaself-timedwrite  
basedupona decisionwhichcanbe leftuntilthe endofthe write cycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothesystem  
designer,astheIDT71Vx576/578canprovidefourcyclesofdataforasingle  
addresspresentedtotheSRAM. Aninternalburstaddresscounteracceptsthe  
firstcycleaddressfromtheprocessor,initiatingtheaccesssequence.Thefirst  
cycleofoutputdatawillbepipelinedforonecyclebeforeitisavailableonthe  
next rising clock edge. If burst mode operation is selected (ADV=LOW),  
the subsequent three cycles of output data will be available to the user on  
the next three rising clock edges. The order of these three addresses are  
defined by the internal burst counter and the LBO input pin.  
• 128K x 36, 256K x 18 memory configurations  
• Supports high system speed:  
– 200MHz 3.1ns clock access time  
– 183MHz 3.3ns clock access time  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
• Self-timed write cycle with global write control (GW), byte write  
enable (BWE), and byte writes (BWx)  
• 3.3V core power supply  
• Power down controlled by ZZ input  
• 2.5V or 3.3V I/O option  
TheIDT71Vx576/578SRAMsutilizeIDT’slatesthigh-performanceCMOS  
processandarepackagedinaJEDECstandard14mmx20mm100-leadthin  
plastic quad flatpack (TQFP) as well as a 119-lead ball grid array (BGA).  
• Packaged in a JEDEC Standard 100-lead plastic thin quad flatpack  
(TQFP) and 119-lead ball grid array (BGA)  
PIN DESCRIPTION SUMMARY  
A
0
-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
OE  
GW  
0, CS  
1
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW  
(1)  
1
2
, BW  
3
, BW  
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
4876 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71Vx578.  
APRIL 1999  
1
1998 Integrated Device Technology, Inc.  
DSC-4876/2  

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