Datasheet > 存储 > SRAM> IDT71V2558SA166PFI

IDT71V2558SA166PFI

更新时间： 2024-11-15 23:08:19

品牌	Logo	应用领域
艾迪悌 - IDT		计数器静态存储器
页数	文件大小	规格书
28页	1012K
描述
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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128K x 36, 256K x 18

IDT71V2556S

IDT71V2558S

IDT71V2556SA

IDT71V2558SA

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

Features

cycle,andtwocycleslatertheassociateddatacycleoccurs,beitread

or write.

The IDT71V2556/58 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

AClockEnable(CEN)pinallowsoperationoftheIDT71V2556/58to

besuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis

initiated.

TheIDT71V2556/58hasanon-chipburstcounter.Intheburstmode,

theIDT71V2556/58canprovidefourcyclesofdataforasingleaddress

presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe

LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V2556/58 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

◆

128K x 36, 256K x 18 memory configurations

◆

Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

◆

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

◆

complaint)

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Description

TheIDT71V2556/58 are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles

when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT , or Zero Bus

Turnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

PinDescriptionSummary

A -A

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE , CE

Output Enable

R/W

CEN

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

BW , BW , BW , BW

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Te s t Clo c k

Te s t Data Outp ut

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

, V

Supply

Static

4875 tbl 01

OCTOBER 2004

DSC-4875/08

12 3 4 5 6 7...28

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与IDT71V2558SA166PFI相关器件

型号	品牌	获取价格	描述	数据表
IDT71V2558SA200BG	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558SA200BG8	IDT	获取价格	ZBT SRAM, 256KX18, 3.2ns, CMOS, PBGA119
IDT71V2558SA200BGI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558SA200BQ	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558SA200BQI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558SA200PF	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558SA200PFI	IDT	获取价格	128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2558SX100PFI	IDT	获取价格	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP
IDT71V2558SX133PF	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2558SX133PFI	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ

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