IDT71V2546S/XS
128K x 36
3.3V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Pipelined Outputs
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle, andtwocycleslatertheassociateddatacycleoccurs, beitread
or write.
Features
◆
128K x 36 memory configurations
◆
Supports high performance system speed - 150 MHz
The IDT71V2546 contains data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
(3.8 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
cycles
◆
AClockEnable(CEN)pinallowsoperationoftheIDT71V2546tobe
suspended as long as necessary. All synchronous inputs are ignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Internally synchronized output buffer enable eliminates the
need to control OE
◆
Single R/W (READ/WRITE) control pin
◆
Positive clock-edge triggered address, data, and control
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis
initiated.
signal registers for fully pipelined applications
◆
4-word burst capability (interleaved or linear)
◆
Individual byte write (BW1 - BW4) control (May tie active)
◆
Three chip enables for simple depth expansion
◆
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
TheIDT71V2546hasanon-chipburstcounter.Intheburstmode,the
IDT71V2546 can provide four cycles of data for a single address
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
flatpack (TQFP) and 119 ball grid array (BGA)
Description
The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
Thus, theyhavebeengiventhenameZBTTM, orZeroBusTurnaround.
TheIDT71V2546SRAMutilizeIDT's latesthigh-performanceCMOS
process and is packaged in a JEDEC standard 14mm x 20mm 100-pin
thinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA).
PinDescriptionSummary
A0-A16
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE , CE
1
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
ZZ
Synchronous
Synchronous
Static
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
Static
5294 tbl 01
APRIL 2011
1
©2011IntegratedDeviceTechnology,Inc.
DSC-5294/07