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IDT71V2548S133BGG

更新时间： 2024-09-29 06:01:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
28页 496K
描述
ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119

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IDT71V2548S133BGG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：14 X 22 MM, PLASTIC, MS-028AA, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：4.2 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B119JESD-609代码：e1
长度：22 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：2.36 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IDT71V2548S133BGG 数据手册

 浏览型号IDT71V2548S133BGG的Datasheet PDF文件第2页浏览型号IDT71V2548S133BGG的Datasheet PDF文件第3页浏览型号IDT71V2548S133BGG的Datasheet PDF文件第4页浏览型号IDT71V2548S133BGG的Datasheet PDF文件第5页浏览型号IDT71V2548S133BGG的Datasheet PDF文件第6页浏览型号IDT71V2548S133BGG的Datasheet PDF文件第7页 
IDT71V2546S/XS  
IDT71V2548S/XS  
128K x 36, 256K x 18  
3.3V Synchronous ZBT™ SRAMs  
IDT71V2546SA/XSA  
IDT71V2548SA/XSA  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle, andtwocycleslatertheassociateddatacycleoccurs, beitread  
or write.  
◆
128K x 36, 256K x 18 memory configurations  
◆
Supports high performance system speed - 150 MHz  
(3.8 ns Clock-to-Data Access)  
The IDT71V2546/48 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V2546/48to  
besuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
◆
ZBTTM Feature - No dead cycles between write and read  
cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
◆
◆
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)  
Optional Boundary Scan JTAG Interface (IEEE1149.1  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis  
initiated.  
◆
◆
◆
◆
◆
complaint)  
TheIDT71V2546/48hasanon-chipburstcounter.Intheburstmode,  
theIDT71V2546/48canprovidefourcyclesofdataforasingleaddress  
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe  
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence. The ADV/LD signal is used to load a new external address  
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =  
HIGH).  
The IDT71V2546/48 SRAMs utilize IDT's latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
◆
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine  
pitch ball grid array  
Description  
TheIDT71V2546/48 are3.3Vhigh-speed4,718,592-bit(4.5Mega-  
bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles  
when turning the bus around between reads and writes, or writes and  
reads. Thus, they have been given the name ZBTTM, or Zero Bus  
Turnaround.  
PinDescriptionSummary  
A
0-A17  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
TMS  
TDI  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Test Mode Select  
Test Data Input  
Synchronous  
Static  
Synchronous  
Synchronous  
N/A  
TCK  
TDO  
TRST  
ZZ  
Test Clock  
Test Data Output  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Static  
JTAG Reset (Optional)  
Sleep Mode  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5294 tbl 01  
FEBRUARY 2007  
1
©2007IntegratedDeviceTechnology,Inc.  
DSC-5294/05  
1234567...28

中文翻译

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与IDT71V2548S133BGG相关器件

型号 品牌 获取价格 描述 数据表
IDT71V2548S133BGI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2548S133BGI8 IDT

获取价格

 		ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
IDT71V2548S133BQ IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2548S133BQGI IDT

获取价格

 		ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
IDT71V2548S133BQI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2548S133PF IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
IDT71V2548S133PF8 IDT

获取价格

 		ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2548S133PF9 IDT

获取价格

 		ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2548S133PFGI IDT

获取价格

 		ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
IDT71V2548S133PFI IDT

获取价格

 		128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

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