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IDT71V016S20PH PDF预览

IDT71V016S20PH

更新时间: 2024-01-13 05:36:01
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
9页 81K
描述
3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)

IDT71V016S20PH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.400 INCH, PLASTIC, SOJ-44
针数:44Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.63最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J44
JESD-609代码:e0长度:28.575 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ44,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:3.683 mm
最大待机电流:0.007 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.12 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

IDT71V016S20PH 数据手册

 浏览型号IDT71V016S20PH的Datasheet PDF文件第2页浏览型号IDT71V016S20PH的Datasheet PDF文件第3页浏览型号IDT71V016S20PH的Datasheet PDF文件第4页浏览型号IDT71V016S20PH的Datasheet PDF文件第5页浏览型号IDT71V016S20PH的Datasheet PDF文件第6页浏览型号IDT71V016S20PH的Datasheet PDF文件第7页 
3.3V CMOS Static RAM  
1 Meg (64K x 16-Bit)  
IDT71V016  
Features  
Description  
64K x 16 advanced high-speed CMOS Static RAM  
Commercial (0° to +70°C) and Industrial (–40°C to +85°C)  
Equal access and cycle times  
The IDT71V016 is a 1,048,576-bit high-speed Static RAM  
organized as 64K x 16. It is fabricated using IDTs high-perfomance,  
high-reliability CMOS technology. This state-of-the-art technology,  
combined with innovative circuit design techniques, provides a  
cost-effective solution for high-speed memory needs.  
— Commercial and Industrial: 15/20ns  
One Chip Select plus one Output Enable pin  
Bidirectional data inputs and outputs directly  
LVTTL-compatible  
Low power consumption via chip deselect  
Upper and Lower Byte Enable Pins  
Single 3.3V (±0.3V) power supply  
The IDT71V016 has an output enable pin which operates as fast  
as 7ns, with address access times as fast as 12ns. All bidirectional  
inputs and outputs of the IDT71V016 are LVTTL-compatible and  
operationisfromasingle3.3Vsupply.Fullystaticasynchronouscircuitry  
is used, requiring no clocks or refresh for operation.  
Available in 44-pin Plastic SOJ and 44-pin TSOP  
package.  
The IDT71V016 is packaged in a JEDEC standard 44-pin  
Plastic SOJ and 44-pin TSOP Type II.  
Functional Block Diagram  
Output  
Enable  
Buffer  
OE  
Address  
Buffers  
Row / Column  
Decoders  
A0 - A15  
I/O15  
High  
Byte  
I/O  
8
8
Chip  
Enable  
Buffer  
CS  
Buffer  
I/O8  
Sense  
Amps  
and  
Write  
Drivers  
16  
64K x 16  
Memory  
Array  
Write  
Enable  
Buffer  
WE  
I/O7  
Low  
Byte  
I/O  
8
8
Buffer  
I/O0  
BHE  
BLE  
Byte  
Enable  
Buffers  
3211 drw 01  
AUGUST 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-3211/08  

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