HIGH-SPEED
IDT7134SA/LA
4K x 8 DUAL-PORT
STATIC SRAM
Description
Features
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The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designedtobeusedinsystemswhereon-chiphardwareportarbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.
High-speed access
Military: 25/35/45/55/70ns (max.)
Industrial: 55ns (max.)
Commercial: 20/25/35/45/55/70ns (max.)
Low-power operation
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IDT7134SA
TheIDT7134providestwoindependentportswithseparatecontrol,
address, and I/O pins that permit independent, asynchronous access
forreadsorwritestoanylocationinmemory.Itistheusersresponsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,
controlled by CE, permits the on-chip circuitry of each port to enter a
very low standby power mode.
FabricatedusingIDTsCMOShigh-performancetechnology,these
Dual-Port typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery.
Active: 700mW (typ.)
Standby: 5mW (typ.)
IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Fully asynchronous operation from either port
Battery backup operation2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
Military product compliant to MIL-PRF-38535 QML
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Industrial temperature range (40°C to +85°C) is available for
The IDT7134 is packaged on either a sidebraze or plastic 48-pin
DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade
product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML, making it ideally suited to military temperature
applicationsdemandingthehighestlevelofperformanceandreliability.
selected speeds
Functional Block Diagram
R/WL
CEL
R/WR
CER
L
OE
OER
COLUMN
COLUMN
I/O0L- I/O7L
I/O0R- I/O7R
I/O
I/O
LEFT SIDE
RIGHT SIDE
ADDRESS
DECODE
LOGIC
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
A0L- A11L
A0R- A11R
2720 drw 01
JUNE 1999
1
DSC-2720/9