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IDT70V9279S9PRFGI PDF预览

IDT70V9279S9PRFGI

更新时间: 2024-11-18 13:02:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
19页 337K
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IDT70V9279S9PRFGI 数据手册

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HIGH-SPEED 3.3V  
32/16K x 16  
IDT70V9279/69S/L  
SYNCHRONOUS  
DUAL-PORT STATIC RAM  
Features:  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
4ns setup to clock and 1ns hold on all control, data,  
and address inputs  
– Commercial:6.5/7.5/9/12/15ns(max.)  
– Industrial: 7.5ns (max.)  
Low-power operation  
Data input, address, and control registers  
Fast 6.5ns clock to data out in the Pipelined output mode  
– IDT70V9279/69S  
Active:429mW(typ.)  
Standby: 3.3mW (typ.)  
– IDT70V9279/69L  
Active:429mW(typ.)  
Standby: 1.32mW (typ.)  
– Self-timedwriteallowsfastcycletime  
– 10ns cycle time, 100MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Flow-through or Pipelined output mode on either port via  
the FT/PIPE pin  
Counter enable and reset features  
Available in a 128-pin Thin Quad Flatpack (TQFP) package  
FunctionalBlockDiagram  
R/  
W
L
L
R/  
W
R
R
UB  
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
OE  
L
L
LB  
OE  
R
R
1a 0a  
a
0a 1a  
1b 0b  
0b 1b  
0/1  
b
0/1  
FT/PIPE  
L
a
b
FT/PIPER  
,
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
(1)  
(1)  
A
A
14R  
A
14L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
0R  
CLK  
A
0L  
MEMORY  
ARRAY  
R
R
CLK  
L
L
ADS  
ADS  
CNTEN  
R
CNTEN  
L
L
CNTRST  
CNTRST  
R
3743 drw 01  
NOTE:  
1. A14X is a NC for IDT70V9269.  
MAY 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC 3743/8  

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