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IDT70V9079SPFI PDF预览

IDT70V9079SPFI

更新时间: 2024-10-29 21:04:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
15页 206K
描述
Dual-Port SRAM, 32KX8, CMOS, PQFP100, TQFP-100

IDT70V9079SPFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.82
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm内存密度:262144 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT70V9079SPFI 数据手册

 浏览型号IDT70V9079SPFI的Datasheet PDF文件第2页浏览型号IDT70V9079SPFI的Datasheet PDF文件第3页浏览型号IDT70V9079SPFI的Datasheet PDF文件第4页浏览型号IDT70V9079SPFI的Datasheet PDF文件第5页浏览型号IDT70V9079SPFI的Datasheet PDF文件第6页浏览型号IDT70V9079SPFI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 32K x 8  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
PRELIMINARY  
IDT70V9079S/L  
Features:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial: 9/12/15ns (max.)  
Low-power operation  
additional logic  
Full synchronous operation on both ports  
– 4ns setup to clock and 1ns hold on all control, data, and  
addressinputs  
– Data input, address, and control registers  
– IDT70V9079S  
– Fast 9ns clock to data out in the Pipelined output mode  
Active: 429mW (typ.)  
– Self-timedwriteallowsfastcycletime  
Standby: 3.3mW (typ.)  
– IDT70V9079L  
– 15ns cycle time, 66MHz operation in the Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Active: 429mW (typ.)  
Standby: 1.32mW (typ.)  
Flow-Through or Pipelined output mode on Right Port via  
the FT/PIPER pin  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
Available in a 100 pin Thin Quad Flatpack (TQFP)  
FunctionalBlockDiagram  
R/WL  
OEL  
R/WR  
OER  
CE0R  
CE1R  
CE0L  
CE1L  
1
0
0/1  
1
0
0/1  
FT/PIPER  
I/O0R - I/O7R  
I/O0L - I/O7L  
I/O  
I/O  
Control  
Control  
A14R  
A14L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A0R  
A0L  
CLKL  
ADSL  
CNTENL  
CLKR  
ADSR  
CNTENR  
CNTRSTR  
CNTRSTL  
3753 drw 01  
JUNE 1999  
1
DSC 3753/4  
©1999IntegratedDeviceTechnology,Inc.  

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