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IDT70V9089L12PFGI PDF预览

IDT70V9089L12PFGI

更新时间: 2024-10-29 21:11:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 197K
描述
Dual-Port SRAM, 64KX8, 25ns, CMOS, PQFP100, TQFP-100

IDT70V9089L12PFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.48
最长访问时间:25 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:100字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX8封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT70V9089L12PFGI 数据手册

 浏览型号IDT70V9089L12PFGI的Datasheet PDF文件第2页浏览型号IDT70V9089L12PFGI的Datasheet PDF文件第3页浏览型号IDT70V9089L12PFGI的Datasheet PDF文件第4页浏览型号IDT70V9089L12PFGI的Datasheet PDF文件第5页浏览型号IDT70V9089L12PFGI的Datasheet PDF文件第6页浏览型号IDT70V9089L12PFGI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 64K x 8  
SYNCHRONOUS  
PRELIMINARY  
IDT70V9089S/L  
DUAL-PORT STATIC RAM  
Features:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:9/12/15ns (max.)  
Low-power operation  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
4ns setup to clock and 1ns hold on all control, data, and  
addressinputs  
IDT70V9089S  
Data input, address, and control registers  
Fast 9ns clock to data out in the Pipelined output mode  
Active:429mW(typ.)  
Standby: 3.3mW (typ.)  
Self-timedwriteallowsfastcycletime  
IDT70V9089L  
15nscycletime,66MHzoperationinthePipelinedoutputmode  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Active:429mW(typ.)  
Standby: 660mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pin  
Counter enable and reset features  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Available in a 100 pin Thin Quad Flatpack (TQFP) package  
FunctionalBlockDiagram  
R/WL  
OEL  
R/WR  
OE  
R
CE0L  
CE1L  
CE0R  
CE1R  
1
1
0
0
0/1  
0/1  
1
0
1
0
0/1  
0/1  
FT/PIPEL  
FT/PIPER  
I/O0L - I/O7L  
I/O0R - I/O7R  
I/O  
I/O  
Control  
Control  
A15R  
A15L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A0R  
A0L  
CLKR  
ADSR  
CNTENR  
CLKL  
ADSL  
CNTENL  
CNTRSTL  
CNTRSTR  
3750 drw 01  
MARCH 2000  
1
DSC 3750/6  
©2000IntegratedDeviceTechnology,Inc.  

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