Datasheet > 存储 > SRAM> IDT70V27S35G

IDT70V27S35G

更新时间： 2024-10-26 22:37:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	192K
描述
HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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IDT70V27S35G 数据手册

HIGH-SPEED 3.3V

32K x 16 DUAL-PORT

STATIC RAM

IDT70V27S/L

◆

Features:

◆

IDT70V27 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin

Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA

(fpBGA)

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Industrial:35ns (max.)

◆

– Commercial:15/20/25/35/55ns(max.)

Low-power operation

◆

– IDT70V27S

Active:500mW(typ.)

Standby: 3.3mW (typ.)

– IDT70V27L

◆

Active:500mW(typ.)

Standby:660µW(typ.)

Separate upper-byte and lower-byte control for bus

◆

matching capability

Dual chip enables allow for depth expansion without

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

◆

external logic

FunctionalBlockDiagram

R/WL

UBL

R/WR

UBR

CE0L

CE0R

CE1L

CE1R

OER

LBR

OEL

LBL

I/O8-15L

I/O0-7L

I/O8-15R

I/O0-7R

I/O

Control

I/O

Control

(1,2)

BUSY

BUSYR

32Kx16

A14R

A14L

A0L

Address

Decoder

Address

Decoder

MEMORY

ARRAY

70V27

A0R

A14L

A14R

A0R

CE0R

A0L

CE0L

CE1L

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE1R

OER

OEL

R/WL

R/WR

SEM

INT

SEMR

(2)

INTR

M/S⁽²⁾

NOTES:

3603 drw 01

1) BUSY is an input as a Slave (M/S=V^IL) and an output as a Master (M/S=VIH).

2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2001

6.011

DSC 3603/7

12 3 4 5 6 7...22

中文翻译

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