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IDT70T651S12DR8 PDF预览

IDT70T651S12DR8

更新时间: 2024-11-26 07:44:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
27页 231K
描述
Multi-Port SRAM, 256KX36, 12ns, CMOS, PQFP208

IDT70T651S12DR8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
风险等级:5.6最长访问时间:12 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G208
JESD-609代码:e0内存密度:9437184 bit
内存集成电路类型:MULTI-PORT SRAM内存宽度:36
端口数量:2端子数量:208
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP208,1.2SQ,20
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5,2.5/3.3 V认证状态:Not Qualified
最大待机电流:0.01 A最小待机电流:2.4 V
子类别:SRAMs最大压摆率:0.355 mA
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

IDT70T651S12DR8 数据手册

 浏览型号IDT70T651S12DR8的Datasheet PDF文件第2页浏览型号IDT70T651S12DR8的Datasheet PDF文件第3页浏览型号IDT70T651S12DR8的Datasheet PDF文件第4页浏览型号IDT70T651S12DR8的Datasheet PDF文件第5页浏览型号IDT70T651S12DR8的Datasheet PDF文件第6页浏览型号IDT70T651S12DR8的Datasheet PDF文件第7页 
IDT70T651/9S  
HIGH-SPEED 2.5V  
256/128K x 36  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
WITH 3.3V 0R 2.5V INTERFACE  
On-chip port arbitration logic  
Features  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:8/10/12/15ns(max.)  
Industrial:10/12ns (max.)  
Sleep Mode Inputs on both ports  
RapidWrite Mode simplifies high-speed consecutive write  
Supports JTAG features compliant to IEEE 1149.1  
Single 2.5V (±100mV) power supply for core  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad  
Flatpack and 208-ball fine pitch Ball Grid Array.  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
cycles  
Dual chip enables allow for depth expansion without  
external logic  
IDT70T651/9 easily expands data bus width to 72 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
Green parts available, see ordering information  
Functional Block Diagram  
BE3L  
BE3R  
BE2R  
BE2L  
BE1L  
BE0L  
BE1R  
BE0R  
R/WL  
R/WR  
B B B B  
E E E E  
B
E
3
B B B  
E E E  
2 1 0  
0
L
1
L
2
L
3
L
CE0L  
CE1L  
CE0R  
CE1R  
R R R R  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
Dout0-8_R  
Dout9-17_R  
Dout18-26_R  
Dout27-35_R  
256/128K x 36  
MEMORY  
ARRAY  
I/O0L- I/O35L  
Di n_L  
Di n_R  
I/O0R -I/O35R  
(1)  
A
17R  
0R  
(1)  
17L  
Address  
Decoder  
A
Address  
Decoder  
ADDR_L  
ADDR_R  
A
A0L  
CE0L  
CE1L  
ARBITRATION  
CE0R  
CE1R  
TDI  
TC K  
TMS  
TRST  
JTAG  
INTERRUPT  
SEMAPHORE  
LOGIC  
TD O  
OE  
L
OE  
R
R/WL  
R/W  
R
(2,3)  
(3)  
(2,3)  
R
BUSY  
L
BUSY  
SEM  
M/S  
SEM  
L
R
(3)  
INT  
L
INT  
R
ZZ  
(4)  
(4)  
ZZR  
ZZL  
CONTROL  
LOGIC  
NOTES:  
1. Address A17x is a NC for IDT70T659.  
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
4869 drw 01  
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep  
mode pins themselves (ZZx) are not affected during sleep mode.  
JANUARY 2006  
1
DSC-5632/5  
©2006IntegratedDeviceTechnology,Inc.  

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