Datasheet > IDT70T653M

IDT70T653M

更新时间： 2024-11-24 22:41:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
24页	308K
描述
HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

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中文翻译

获取价格

数据手册

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IDT70T653M 数据手册

HIGH-SPEED 2.5V

PRELIMINARY

IDT70T653M

512K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

Features

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

◆

– Commercial:10/12/15ns(max.)

– Industrial: 12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T653M easily expands data bus width to 72 bits or

more using the Busy Input when cascading more than one

device

◆

Sleep Mode Inputs on both ports

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Includes JTAG functionality

Available in a 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Busy input for port contention management

Interrupt Flags

Functional Block Diagram

BE3L

BE3R

BE2R

BE2L

BE1L

BE0L

BE1R

BE0R

R/WL

R/WR

B B B B

E E E E

B B B

E E E

2 1 0

CE0L

CE0R

R R R R

CE1L

CE1R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

512K x 36

MEMORY

ARRAY

I/O0L- I/O35L

Di n_L

Di n_R

I/O0R -I/O35R

18R

Address

Decoder

18L

Address

Decoder

ADDR_L

ADDR_R

CE0L

CE1L

ARBITRATION

CE0R

CE1R

TDI

TC K

TMS

JTAG

INTERRUPT

SEMAPHORE

LOGIC

TD O

TRST

R/WL

R/W

BUSY

SEM

(1)

INT

CONTROL

LOGIC

(2)

ZZR

NOTES:

1. INT is non-tri-state totem-pole outputs (push-pull).

5679 drw 01

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode

pins themselves (ZZx) are not affected during sleep mode.

NOVEMBER 2003

DSC-5679/2

12 3 4 5 6 7...24

中文翻译

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与IDT70T653M相关器件

型号	品牌	获取价格	描述	数据表
IDT70T653MS10BC	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
IDT70T653MS10BCG	IDT	获取价格	Dual-Port SRAM, 512KX36, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
IDT70T653MS10BCI	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
IDT70T653MS12BC	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
IDT70T653MS12BCG	IDT	获取价格	Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
IDT70T653MS12BCGI	IDT	获取价格	Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREE
IDT70T653MS12BCI	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
IDT70T653MS12BCI8	IDT	获取价格	Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, BGA-256
IDT70T653MS15BC	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
IDT70T653MS15BC8	IDT	获取价格	Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, BGA-256

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