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IDT70T653M

更新时间: 2024-10-28 22:41:03
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
24页 308K
描述
HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

IDT70T653M 数据手册

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HIGH-SPEED 2.5V  
PRELIMINARY  
IDT70T653M  
512K x 36  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
WITH 3.3V 0R 2.5V INTERFACE  
Features  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
– Commercial:10/12/15ns(max.)  
– Industrial: 12ns (max.)  
RapidWrite Mode simplifies high-speed consecutive write  
cycles  
Dual chip enables allow for depth expansion without  
external logic  
IDT70T653M easily expands data bus width to 72 bits or  
more using the Busy Input when cascading more than one  
device  
Sleep Mode Inputs on both ports  
Single 2.5V (±100mV) power supply for core  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Includes JTAG functionality  
Available in a 256-ball Ball Grid Array  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Busy input for port contention management  
Interrupt Flags  
Functional Block Diagram  
BE3L  
BE3R  
BE2R  
BE2L  
BE1L  
BE0L  
BE1R  
BE0R  
R/WL  
R/WR  
B B B B  
E E E E  
B
E
3
B B B  
E E E  
2 1 0  
0
L
1
L
2
L
3
L
CE0L  
CE0R  
R R R R  
CE1L  
CE1R  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
Dout0-8_R  
Dout9-17_R  
Dout18-26_R  
Dout27-35_R  
512K x 36  
MEMORY  
ARRAY  
I/O0L- I/O35L  
Di n_L  
Di n_R  
I/O0R -I/O35R  
A
18R  
0R  
Address  
Decoder  
A
18L  
0L  
Address  
Decoder  
ADDR_L  
ADDR_R  
A
A
CE0L  
CE1L  
ARBITRATION  
CE0R  
CE1R  
TDI  
TC K  
TMS  
JTAG  
INTERRUPT  
SEMAPHORE  
LOGIC  
TD O  
TRST  
OE  
L
OE  
R
R/WL  
R/W  
R
BUSY  
L
BUSY  
R
SEM  
L
SEM  
R
(1)  
L
(1)  
R
INT  
INT  
ZZ  
CONTROL  
LOGIC  
(2)  
(2)  
ZZR  
ZZ  
L
NOTES:  
1. INT is non-tri-state totem-pole outputs (push-pull).  
5679 drw 01  
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode  
pins themselves (ZZx) are not affected during sleep mode.  
NOVEMBER 2003  
1
DSC-5679/2  
©2003IntegratedDeviceTechnology,Inc.  

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