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IDT70T653MS12BC PDF预览

IDT70T653MS12BC

更新时间: 2024-10-28 22:45:15
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
24页 308K
描述
HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE

IDT70T653MS12BC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.23
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:17 mm内存密度:18874368 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端口数量:2端子数量:256
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:2.5,2.5/3.3 V认证状态:Not Qualified
座面最大高度:1.5 mm最大待机电流:0.02 A
最小待机电流:2.4 V子类别:SRAMs
最大压摆率:0.71 mA最大供电电压 (Vsup):2.6 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:17 mmBase Number Matches:1

IDT70T653MS12BC 数据手册

 浏览型号IDT70T653MS12BC的Datasheet PDF文件第2页浏览型号IDT70T653MS12BC的Datasheet PDF文件第3页浏览型号IDT70T653MS12BC的Datasheet PDF文件第4页浏览型号IDT70T653MS12BC的Datasheet PDF文件第5页浏览型号IDT70T653MS12BC的Datasheet PDF文件第6页浏览型号IDT70T653MS12BC的Datasheet PDF文件第7页 
HIGH-SPEED 2.5V  
PRELIMINARY  
IDT70T653M  
512K x 36  
ASYNCHRONOUS DUAL-PORT  
STATIC RAM  
WITH 3.3V 0R 2.5V INTERFACE  
Features  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
– Commercial:10/12/15ns(max.)  
– Industrial: 12ns (max.)  
RapidWrite Mode simplifies high-speed consecutive write  
cycles  
Dual chip enables allow for depth expansion without  
external logic  
IDT70T653M easily expands data bus width to 72 bits or  
more using the Busy Input when cascading more than one  
device  
Sleep Mode Inputs on both ports  
Single 2.5V (±100mV) power supply for core  
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)  
power supply for I/Os and control signals on each port  
Includes JTAG functionality  
Available in a 256-ball Ball Grid Array  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Busy input for port contention management  
Interrupt Flags  
Functional Block Diagram  
BE3L  
BE3R  
BE2R  
BE2L  
BE1L  
BE0L  
BE1R  
BE0R  
R/WL  
R/WR  
B B B B  
E E E E  
B
E
3
B B B  
E E E  
2 1 0  
0
L
1
L
2
L
3
L
CE0L  
CE0R  
R R R R  
CE1L  
CE1R  
OEL  
OER  
Dout0-8_L  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
Dout0-8_R  
Dout9-17_R  
Dout18-26_R  
Dout27-35_R  
512K x 36  
MEMORY  
ARRAY  
I/O0L- I/O35L  
Di n_L  
Di n_R  
I/O0R -I/O35R  
A
18R  
0R  
Address  
Decoder  
A
18L  
0L  
Address  
Decoder  
ADDR_L  
ADDR_R  
A
A
CE0L  
CE1L  
ARBITRATION  
CE0R  
CE1R  
TDI  
TC K  
TMS  
JTAG  
INTERRUPT  
SEMAPHORE  
LOGIC  
TD O  
TRST  
OE  
L
OE  
R
R/WL  
R/W  
R
BUSY  
L
BUSY  
R
SEM  
L
SEM  
R
(1)  
L
(1)  
R
INT  
INT  
ZZ  
CONTROL  
LOGIC  
(2)  
(2)  
ZZR  
ZZ  
L
NOTES:  
1. INT is non-tri-state totem-pole outputs (push-pull).  
5679 drw 01  
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode  
pins themselves (ZZx) are not affected during sleep mode.  
NOVEMBER 2003  
1
DSC-5679/2  
©2003IntegratedDeviceTechnology,Inc.  

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