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IDT70T3539MS133BC8 PDF预览

IDT70T3539MS133BC8

更新时间: 2024-10-29 14:51:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 414K
描述
Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, BGA-256

IDT70T3539MS133BC8 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.25
Is Samacsys:N最长访问时间:15 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:S-PBGA-B256
JESD-609代码:e0长度:17 mm
内存密度:18874368 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端口数量:2
端子数量:256字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5,2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.5 mm
最大待机电流:0.02 A最小待机电流:2.4 V
子类别:SRAMs最大压摆率:0.74 mA
最大供电电压 (Vsup):2.6 V最小供电电压 (Vsup):2.4 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:20宽度:17 mm
Base Number Matches:1

IDT70T3539MS133BC8 数据手册

 浏览型号IDT70T3539MS133BC8的Datasheet PDF文件第2页浏览型号IDT70T3539MS133BC8的Datasheet PDF文件第3页浏览型号IDT70T3539MS133BC8的Datasheet PDF文件第4页浏览型号IDT70T3539MS133BC8的Datasheet PDF文件第5页浏览型号IDT70T3539MS133BC8的Datasheet PDF文件第6页浏览型号IDT70T3539MS133BC8的Datasheet PDF文件第7页 
HIGH-SPEED 2.5V  
512K x 36  
IDT70T3539M  
SYNCHRONOUS  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Features:  
– Data input, address, byte enable and control registers  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed data access  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Dual Cycle Deselect (DCD) for Pipelined Output Mode  
2.5V (±100mV) power supply for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.)  
– Industrial: 4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Interrupt and Collision Detection Flags  
Full synchronous operation on both ports  
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)  
– Fast 3.6ns clock to data out  
Includes JTAG functionality  
Industrial temperature range (-40°C to +85°C) is  
available at 133MHz  
Available in a 256-pin Ball Grid Array (BGA)  
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 166MHz  
FunctionalBlockDiagram  
BE3R  
BE3L  
BE2L  
BE1L  
BE0L  
BE2R  
BE1R  
BE0R  
FT/PIPE  
L
0a 1a  
a
0b 1b  
b
0c 1c  
c
0d 1d  
d
1d 0d  
d
1c 0c  
c
1b 0b  
b
1a 0a  
a
FT/PIPER  
1/0  
1/0  
R/WL  
R/WR  
CE0L  
CE0R  
1
1
CE1R  
CE1L  
0
0
B
B B B  
B
B B B  
1/0  
1/0  
W W W W W W W W  
0
L
1
L
2
L
3
L
3
R
2
1
R
0
R
R
OE  
R
OE  
L
Dout0-8_L  
Dout0-8_R  
Dout9-17_R  
Dout18-26_R  
Dout27-35_R  
Dout9-17_L  
Dout18-26_L  
Dout27-35_L  
,
1d 0d 1c 0c  
1b 0b 1a 0a  
0a 1a 0b 1b  
0c 1c 0d 1d  
d c b a  
0/1  
0/1  
FT/PIPE  
R
FT/PIPE  
L
a bc d  
512K x 36  
MEMORY  
ARRAY  
I/O0L - I/O35L  
I/O0R - I/O35R  
Din_L  
Din_R  
,
CLK  
R
CLK  
L
A
18R  
A
18L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
0L  
REPEAT  
ADS  
CNTEN  
A
0R  
REPEAT  
ADS  
CNTEN  
ADDR_R  
ADDR_L  
L
R
R
L
R
L
TDI  
TCK  
TMS  
TRST  
INTERRUPT  
CE  
CE1  
0
R
CE  
0
L
JTAG  
COLLISION  
DETECTION  
LOGIC  
R
CE1  
TDO  
L
R/  
W
L
R/W  
R
COL  
L
COL  
R
INT  
L
INT  
R
(1)  
(1)  
ZZR  
ZZ  
CONTROL  
LOGIC  
ZZ  
L
5678 drw 01  
NOTE:  
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and  
the sleep mode pins themselves (ZZx) are not affected during sleep mode.  
MAY 2004  
1
DSC 5678/6  
©2004IntegratedDeviceTechnology,Inc.  

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