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IDT709199L12PFG PDF预览

IDT709199L12PFG

更新时间: 2024-11-07 05:06:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
15页 163K
描述
Dual-Port SRAM, 128KX9, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT709199L12PFG 数据手册

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IDT709199L  
HIGH-SPEED 128K x 9  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns (max.)  
Industrial:9ns (max.)  
additional logic  
Full synchronous operation on both ports  
– 4ns setup to clock and 0ns hold on all control, data, and  
address inputs  
Data input, address, and control registers  
– Fast 7.5ns clock to data out in the Pipelined output mode  
– Self-timed write allows fast cycle time  
Low-power operation  
IDT709199L  
Active: 1.2W (typ.)  
Standby: 2.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
– 12ns cycle time, 83MHz operation in Pipelined output mode  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
Functional Block Diagram  
R/W  
L
R/W  
R
OEL  
OER  
CE0R  
CE1R  
CE0L  
CE1L  
1
0
1
0
0/1  
0/1  
0
1
1
FT/PIPE  
L
0/1  
0
0/1  
FT/PIPE  
R
I/O0L - I/O8L  
I/O0R - I/O8R  
I/O  
Control  
I/O  
Control  
A
16L  
A
16R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
C0LRK  
R
R
A
0L  
L
L
CLK  
ADS  
ADS  
CNTEN  
R
CNTEN  
L
CNTRST  
R
CNTRST  
L
4847 drw 01  
NOVEMBER 2001  
1
DSC-4847/4  
©2001IntegratedDeviceTechnology,Inc.  

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