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IDT709199L9PFG PDF预览

IDT709199L9PFG

更新时间: 2024-11-06 13:08:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
15页 179K
描述
Dual-Port SRAM, 128KX9, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT709199L9PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:14 X 14 MM, 1.40 MM HEIGHT, TQFP-100针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:20 ns其他特性:PIPELINED OR FLOW-THROUGH ARCHITECTURE
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm内存密度:1179648 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX9封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT709199L9PFG 数据手册

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IDT709199L  
HIGH-SPEED 128K x 9  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial: 7.5/9/12ns (max.)  
Low-power operation  
Full synchronous operation on both ports  
4ns setup to clock and 0ns hold on all control, data, and  
address inputs  
Data input, address, and control registers  
Fast 7.5ns clock to data out in the Pipelined output mode  
Self-timed write allows fast cycle time  
IDT709199L  
Active: 1.2W (typ.)  
Standby: 2.5mW (typ.)  
12ns cycle time, 83MHz operation in Pipelined output mode  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
Functional Block Diagram  
R/WL  
OEL  
R/WR  
OER  
CE0R  
CE1R  
CE0L  
1
1
0
CE1L  
0
0/1  
0/1  
0
1
1
FT/PIPEL  
0/1  
0
0/1  
FT/PIPER  
I/O0L - I/O8L  
I/O0R - I/O8R  
I/O  
Control  
I/O  
Control  
A16L  
A16R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A0R  
A0L  
CLKR  
CLKL  
ADSR  
ADSL  
CNTENL  
CNTENR  
CNTRSTR  
CNTRSTL  
4847 drw 01  
JANUARY 2001  
1
DSC-4847/3  
©2000IntegratedDeviceTechnology,Inc.  

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