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IDT7006S20PFI8 PDF预览

IDT7006S20PFI8

更新时间: 2024-11-09 21:22:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
20页 170K
描述
Application Specific SRAM, 16KX8, 20ns, CMOS, PQFP64

IDT7006S20PFI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
风险等级:5.27最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G64
JESD-609代码:e0内存密度:131072 bit
内存集成电路类型:APPLICATION SPECIFIC SRAM内存宽度:8
湿度敏感等级:3端口数量:2
端子数量:64字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP64,.6SQ,32封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified最大待机电流:0.03 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.37 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
Base Number Matches:1

IDT7006S20PFI8 数据手册

 浏览型号IDT7006S20PFI8的Datasheet PDF文件第2页浏览型号IDT7006S20PFI8的Datasheet PDF文件第3页浏览型号IDT7006S20PFI8的Datasheet PDF文件第4页浏览型号IDT7006S20PFI8的Datasheet PDF文件第5页浏览型号IDT7006S20PFI8的Datasheet PDF文件第6页浏览型号IDT7006S20PFI8的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7006S/L  
16K x 8 DUAL-PORT  
STATIC RAM  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Devices are capable of withstanding greater than 2001V  
electrostatic discharge  
Battery backup operation2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin  
TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speed  
Green parts available, see ordering information  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:20/25/35/55/70ns(max.)  
Industrial:55ns (max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
IDT7006S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7006L  
Active:700mW(typ.)  
Standby: 1mW (typ.)  
IDT7006 easily expands data bus width to 16 bits or more  
using the Master/Slave select when cascading more than  
one device  
FunctionalBlockDiagram  
OE  
R
OEL  
CE  
R/W  
R
CE  
L
R/W  
L
R
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
BUSY  
R
A
13L  
A
13R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
0R  
14  
14  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
R
L
R
L
SEM  
R
SEM (2)  
L
M/S  
(2)  
INT  
L
INTR  
2739 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JANUARY 2006  
1
©2006IntegratedDeviceTechnology,Inc.  
DSC 2739/15  

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