Datasheet > IDT5T9306_08

IDT5T9306_08

更新时间： 2022-11-08 10:06:49

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
14页	214K
描述
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER? II

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IDT5T9306_08 数据手册

2.5V LVDS 1:6 CLOCK BUFFER

TERABUFFER™ II

IDT5T9306

DESCRIPTION:

FEATURES:

TheIDT5T93062.5Vdifferential clockbufferisauser-selectabledifferential

inputtosixLVDSoutputs. ThefanoutfromadifferentialinputtosixLVDSoutputs

reduces loading on the preceding driver and provides an efficient clock

distributionnetwork. TheIDT5T9306canactasatranslatorfromadifferential

HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to

LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to

translate to LVDS outputs. The redundant input capability allows for an

asynchronouschange-over fromaprimaryclocksourcetoasecondaryclock

source. SelectablereferenceinputsarecontrolledbySEL.

• Guaranteed Low Skew < 25ps (max)

• Very low duty cycle distortion < 125ps (max)

• High speed propagation delay < 1.75ns (max)

• Additive phase jitter, RMS 0.159ps (typical) @ 125MHz

• Up to 1GHz operation

• Selectable inputs

• Hot insertable and over-voltage tolerant inputs

• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),

CML, or LVDS input interface

TheIDT5T9306outputscanbeasynchronouslyenabled/disabled. When

disabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiplepower

and grounds reduce noise.

• Selectable differential inputs to six LVDS outputs

• Power-down mode

• 2.5V VDD

• Available in VFQFPN package

APPLICATIONS:

• Clock distribution

FUNCTIONALBLOCKDIAGRAM

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

OUTPUT

CONTROL

SEL

OUTPUT

CONTROL

IDT^™/ ICS^™LVDS CLOCK BUFFER TERABUFFER™ II

IDT5T9306 REV. B APRIL 15, 2008

12 3 4 5 6 7...14

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