IDT5991A-7JG

更新时间： 2024-01-06 10:12:27

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器逻辑集成电路
页数	文件大小	规格书
8页	68K
描述
PLL Based Clock Driver, 5991 Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, GREEN, PLASTIC, LCC-32

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技术参数
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IDT5991A-7JG 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	PLASTIC, LCC-32	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.72	Is Samacsys：	N
输入调节：	STANDARD	JESD-30 代码：	R-PQCC-J32
JESD-609代码：	e0	长度：	13.97 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.75 ns
座面最大高度：	3.55 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	11.43 mm
最小 fmax：	100 MHz	Base Number Matches：	1

IDT5991A-7JG 数据手册

IDT5991A

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK

EXTERNALFEEDBACK

By providing external feedback, the IDT5991A gives users flexibility

with regard to skew adjustment. The FB signal is compared with the

input REF signal at the phase detector in order to drive the VCO. Phase

differences cause the VCO of the PLL to adjust upwards or downwards

accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.

PLLPROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE

FS = LOW

1/(44 x FNOM)

15 to 35MHz

FS = MID

1/(26 x FNOM)

25 to 60MHz

FS = HIGH

1/(16 x FNOM)

40 to 100MHz

Comments

TimingUnitCalculation(tU)

VCOFrequencyRange(FNOM)^(1,2)

SkewAdjustmentRange⁽³⁾

MaxAdjustment:

±9.09ns

±49º

±9.23ns

±83º

±9.38ns

±135º

PhaseDegrees

% of Cycle Time

±14%

tU = 1.52ns

tU = 0.91ns

tU = 0.76ns

—

±23%

±37%

—

Example 1, FNOM = 15MHz

Example 2, FNOM = 25MHz

Example 3, FNOM = 30MHz

Example 4, FNOM = 40MHz

Example 5, FNOM = 50MHz

Example 6, FNOM = 80MHz

—

tU = 1.54ns

tU = 1.28ns

tU = 0.96ns

tU = 0.77ns

—

tU = 1.56ns

tU = 1.25ns

tU = 0.78ns

—

NOTES:

1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on

input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.

2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the

higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected

to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided

output as the FB input.

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example

if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range

applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.

CONTROLSUMMARYTABLEFORFEEDBACKSIGNALS

nF1:0

LL⁽¹⁾

Skew (Pair #1, #2)

Skew (Pair #3)

Divide by 2

–6tU

Skew (Pair #4)

Divide by 2

–6tU

–4tU

–3tU

–2tU

–4tU

–1tU

–2tU

M H

Zero Skew

1tU

Zero Skew

2tU

Zero Skew

2tU

4tU

H M

H H

3tU

6tU

Inverted⁽²⁾

4tU

Divide by 4

NOTES:

1. LL disables outputs if TEST = MID and GND/sOE = HIGH.

2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ/PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ/PE = LOW.

1 234 5 6 7 8

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与IDT5991A-7JG相关器件

型号	品牌	描述	获取价格	数据表
IDT5991A-7JI	IDT	PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK	获取价格
IDT5991A-7JRI	IDT	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32	获取价格
IDT59920-7SO	IDT	LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.	获取价格
IDT59920-7SOI	IDT	LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.	获取价格
IDT59920A	IDT	LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.	获取价格
IDT59920A-2SO	IDT	LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.	获取价格

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