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IDT23S08T-3DCG PDF预览

IDT23S08T-3DCG

更新时间: 2024-10-04 13:00:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
6页 51K
描述
PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, GREEN, SOIC-16

IDT23S08T-3DCG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.59系列:23S
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9314 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:16实输出次数:8
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.4 ns
座面最大高度:1.7272 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.937 mm
最小 fmax:133.3 MHzBase Number Matches:1

IDT23S08T-3DCG 数据手册

 浏览型号IDT23S08T-3DCG的Datasheet PDF文件第2页浏览型号IDT23S08T-3DCG的Datasheet PDF文件第3页浏览型号IDT23S08T-3DCG的Datasheet PDF文件第4页浏览型号IDT23S08T-3DCG的Datasheet PDF文件第5页浏览型号IDT23S08T-3DCG的Datasheet PDF文件第6页 
2.5V ZERO DELAY CLOCK  
MULTIPLIER, SPREAD  
IDT23S08T  
ADVANCE  
INFORMATION  
SPECTRUM COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution for Applications ranging  
from 10MHz to 133MHz operating frequency  
• Distributes one clock input to two banks of four outputs  
• Separate output enable for each output bank  
• External feedback (FBK) pin is used to synchronize the outputs  
to the clock input  
The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It  
isdesignedtoaddresshigh-speedclockdistributionandmultiplicationapplica-  
tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming  
clockandtheoutputclock, operablewithintherangeof10to133MHz.  
TheIDT23S08Thastwobanksoffouroutputseachthatarecontrolledvia  
twoselectaddresses.Byproperselectionofinputaddresses,bothbankscan  
beputintri-statemode.Intestmode,thePLListurnedoff,andtheinputclock  
directlydrivestheoutputsforsystemtestingpurposes. Intheabsenceofan  
inputclock, theIDT23S08Tenterspowerdown. Inthismode, thedevicewill  
drawlessthan12µA,andtheoutputsaretri-stated.  
• Output Skew <200 ps  
• Low jitter <200 ps cycle-to-cycle  
• 1/2x, 1x, 2x, 4x output options (see table):  
– IDT23S08T-1 1x  
– IDT23S08T-2 1x, 2x  
– IDT23S08T-3 2x, 4x  
– IDT23S08T-4 2x  
The IDT23S08T is available in six unique configurations for both pre-  
scaling and multiplication of the Input REF Clock. (See available options  
table.)  
– IDT23S08T-5 1/2x  
• No external RC network required  
• Operates at 2.5V VDD  
ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser  
tocontrolthedelaybetweentheinputclockandtheoutputs.  
TheIDT23S08TischaracterizedforCommercialoperation.  
• Spread spectrum compatible  
• Available in SOIC package  
FUNCTIONALBLOCKDIAGRAM  
(-3, -4)  
16  
2
FBK  
REF  
2
CLKA1  
PLL  
1
2
3
(-5)  
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
9
S2  
S1  
Control  
Logic  
2
(-2, -3)  
6
CLKB1  
CLKB2  
CLKB3  
CLKB4  
7
10  
11  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
NOVEMBER 2003  
1
c
2003 Integrated Device Technology, Inc.  
DSC - 6510/4  

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