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ICY7C1373C-100BGI PDF预览

ICY7C1373C-100BGI

更新时间： 2024-11-13 22:22:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
33页 762K
描述
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

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中文翻译

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ICY7C1373C-100BGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.88最长访问时间：8.5 ns
其他特性：FLOW-THROUGH ARCHITECTUREJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：18功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：2.4 mm最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

ICY7C1373C-100BGI 数据手册

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CY7C1371C  
CY7C1373C  
18-Mbit (512K x 36/1M x 18) Flow-Through  
SRAM with NoBL™ Architecture  
Functional Description[1]  
Features  
• No Bus Latency™ (NoBL™) architecture eliminates  
The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18  
Synchronous Flow-through Burst SRAM designed specifically  
to support unlimited true back-to-back Read/Write operations  
without the insertion of wait states. The CY7C1371C/  
CY7C1373C is equipped with the advanced No Bus Latency™  
(NoBL™) logic required to enable consecutive Read/Write  
operations with data being transferred on every clock cycle.  
This feature dramatically improves the throughput of data  
through the SRAM, especially in systems that require frequent  
Write-Read transitions.  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
Write operations are controlled by the two or four Byte Write  
Select (BWX) and a Write Enable (WE) input. All writes are  
conducted with on-chip synchronous self-timed write circuitry.  
Three synchronous Chip Enables (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
dead cycles between write and read cycles  
• Can support up to 133-MHz bus operations with zero  
wait states  
— Data is transferred on every clock  
• Pin compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
• 3.3V/2.5V I/O power supply  
• Fast clock-to-output times  
— 6.5 ns (for 133-MHz device)  
— 7.5 ns (for 117-MHz device)  
— 8.5 ns (for 100-MHz device)  
• Clock Enable (CEN) pin to enable clock and suspend  
operation  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• OfferedinJEDEC-standard100TQFP,119-BallBGAand  
165-Ball fBGA packages  
• Three chip enables for simple depth expansion  
• Automatic Power-down feature available using ZZ  
mode or CE deselect  
• JTAG boundary scan for BGA and fBGA packages  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Selection Guide  
133 MHz  
117 MHz  
7.5  
100 MHz  
8.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
6.5  
210  
70  
190  
70  
175  
70  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05234 Rev. *D  
Revised June 03, 2004  
1234567...33

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与ICY7C1373C-100BGI相关器件

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ICY7C1373D-100BGI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture
ICY7C1373D-100BGXI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture
ICY7C1373DV25-100BGI CYPRESS

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 		ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119
ICY7C1373DV25-100BGXI CYPRESS

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 		ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA
ICY7C1387C-167BGI CYPRESS

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 		18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
ICY7C1387CV25-167BGI CYPRESS

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 		18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
ICY7C1387D-167BGI CYPRESS

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 		18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
ICY7C1387D-167BGXI CYPRESS

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 		18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
ICY7C1387DV25-167BGI CYPRESS

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 		Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
ICY7C1387DV25-167BGXI CYPRESS

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 		Standard SRAM, 1MX18, 3.4ns, CMOS, PBGA119

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