Datasheet > ICY7C1373DV25-100BGXI

ICY7C1373DV25-100BGXI

更新时间： 2024-11-07 20:50:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	333K
描述
ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ICY7C1373DV25-100BGXI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA119,7X17,50	针数：	119
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.8
Base Number Matches：	1

ICY7C1373DV25-100BGXI 数据手册

浏览型号ICY7C1373DV25-100BGXI的Datasheet PDF文件第2页

浏览型号ICY7C1373DV25-100BGXI的Datasheet PDF文件第3页

浏览型号ICY7C1373DV25-100BGXI的Datasheet PDF文件第4页

浏览型号ICY7C1373DV25-100BGXI的Datasheet PDF文件第5页

浏览型号ICY7C1373DV25-100BGXI的Datasheet PDF文件第6页

浏览型号ICY7C1373DV25-100BGXI的Datasheet PDF文件第7页

CY7C1371DV25

CY7C1373DV25

PRELIMINARY

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

with NoBL™ Architecture

Features

Functional Description^[1]

• No Bus Latency™ (NoBL™) architecture eliminates

The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/

1 Mbit x 18 Synchronous Flow-through Burst SRAM designed

specifically to support unlimited true back-to-back Read/Write

operations without the insertion of wait states. The

CY7C1371DV25/CY7C1373DV25 is equipped with the

advanced No Bus Latency (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data through the SRAM, especially in

systems that require frequent Write-Read transitions.

dead cycles between write and read cycles

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• Registered inputs for flow-through operation

• Byte Write capability

• Single 2.5V power supply

• 2.5V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 8.5 ns (for 100-MHz device)

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• Offered in JEDEC-standard lead-free 100 TQFP,

119-Ball BGA and 165-Ball fBGA packages

• Three chip enables for simple depth expansion

• Automatic Power-down feature available using ZZ

mode or CE deselect

• JTAG boundary scan for BGA and fBGA packages

• Burst Capability—linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

210

175

Maximum CMOS Standby Current

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05557 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised February 21, 2005

12 3 4 5 6 7...31

中文翻译

下载PDF

与ICY7C1373DV25-100BGXI相关器件

型号	品牌	获取价格	描述	数据表
ICY7C1387C-167BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
ICY7C1387CV25-167BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
ICY7C1387D-167BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
ICY7C1387D-167BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
ICY7C1387DV25-167BGI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
ICY7C1387DV25-167BGXI	CYPRESS	获取价格	Standard SRAM, 1MX18, 3.4ns, CMOS, PBGA119
ICZ0912D05	XPPOWER	获取价格	DC-DC Converter
ICZ0912D12	XPPOWER	获取价格	DC-DC Converter
ICZ0912D15	XPPOWER	获取价格	DC-DC Converter
ICZ0912S05	XPPOWER	获取价格	DC-DC Converter

与ICY7C1373DV25-100BGXI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

16
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

13
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

37
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

34

产品中心

服务支持

精选活动

关于我们

帮助中心

ICY7C1373DV25-100BGXI

ICY7C1373DV25-100BGXI 技术参数

ICY7C1373DV25-100BGXI 数据手册

与ICY7C1373DV25-100BGXI相关器件

与ICY7C1373DV25-100BGXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ICY7C1373DV25-100BGXI

ICY7C1373DV25-100BGXI 技术参数

ICY7C1373DV25-100BGXI 数据手册

与ICY7C1373DV25-100BGXI相关器件

与ICY7C1373DV25-100BGXI相关文章

您还可以找

您在本页遇到什么问题？