Datasheet > ICY7C1373D-100BGI

ICY7C1373D-100BGI

更新时间： 2024-11-13 21:55:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	446K
描述
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture

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PRELIMINARY

CY7C1371D

CY7C1373D

18-Mbit (512K x 36/1M x 18) Flow-Through

SRAM with NoBL™ Architecture

Functional Description^[1]

Features

• No Bus Latency (NoBL) architecture eliminates

The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x

18 Synchronous Flow-through Burst SRAM designed specifi-

cally to support unlimited true back-to-back Read/Write opera-

tions without the insertion of wait states. The CY7C1371D/

CY7C1373D is equipped with the advanced No Bus Latency

(NoBL) logic required to enable consecutive Read/Write

operations with data being transferred on every clock cycle.

This feature dramatically improves the throughput of data

through the SRAM, especially in systems that require frequent

Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two or four Byte Write

Select (BW_X) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

dead cycles between write and read cycles

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

• Pin-compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 3.3V/2.5V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 8.5 ns (for 100-MHz device)

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• OfferedinJEDEC-standardlead-free100TQFP, 119-ball

BGA and 165-ball fBGA packages

• Three chip enables for simple depth expansion

• Automatic Power-down feature available using ZZ

mode or CE deselect

• JTAG boundary scan for BGA and fBGA packages

• Burst Capability—linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

6.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

210

175

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05556 Rev. *A

Revised November 3, 2004

12 3 4 5 6 7...30

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与ICY7C1373D-100BGI相关器件

型号	品牌	获取价格	描述	数据表
ICY7C1373D-100BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture
ICY7C1373DV25-100BGI	CYPRESS	获取价格	ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119
ICY7C1373DV25-100BGXI	CYPRESS	获取价格	ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA
ICY7C1387C-167BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
ICY7C1387CV25-167BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
ICY7C1387D-167BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
ICY7C1387D-167BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
ICY7C1387DV25-167BGI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
ICY7C1387DV25-167BGXI	CYPRESS	获取价格	Standard SRAM, 1MX18, 3.4ns, CMOS, PBGA119
ICZ0912D05	XPPOWER	获取价格	DC-DC Converter

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