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ICY7C1362C-166BGI PDF预览

ICY7C1362C-166BGI

更新时间： 2024-02-11 21:37:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
31页 420K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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ICY7C1362C-166BGI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1.40 HEIGHT, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：220
认证状态：Not Qualified座面最大高度：1.4 mm
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

ICY7C1362C-166BGI 数据手册

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CY7C1360C  
CY7C1362C  
PRELIMINARY  
Pin Definitions  
Name  
I/O  
Description  
A0, A1, A  
Input-  
Synchronous  
Address Inputs used to select one of the address locations. Sampled at the rising  
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled  
active. A , A are fed to the two-bit counter.  
.
1
0
BWA, BWB  
BWC, BWD  
Input-  
Synchronous  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the  
SRAM. Sampled on the rising edge of CLK.  
GW  
Input-  
Synchronous  
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a  
global Write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).  
BWE  
CLK  
CE1  
Input-  
Synchronous  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal  
must be asserted LOW to conduct a Byte Write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment  
the burst counter when ADV is asserted LOW, during a burst operation.  
Input-  
Synchronous  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in  
conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is  
HIGH. CE1 is sampled only when a new external address is loaded.  
CE2  
Input-  
Synchronous  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in  
conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when  
a new external address is loaded.  
[2]  
CE3  
Input-  
Synchronous  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in  
conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package  
version. Not connected for BGA. Where referenced, CE3[2] is assumed active throughout  
this document for BGA. CE3 is sampled only when a new external address is loaded.  
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.  
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are  
three-stated, and act as input data pins. OE is masked during the first clock of a read cycle  
when emerging from a deselected state.  
ADV  
Input-  
Synchronous  
Advance Input signal, sampled on the rising edge of CLK, active LOW. When  
asserted, it automatically increments the address in a burst cycle.  
ADSP  
Input-  
Synchronous  
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.  
When asserted LOW, addresses presented to the device are captured in the address  
registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both  
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.  
Input-  
Synchronous  
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.  
When asserted LOW, addresses presented to the device are captured in the address  
registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both  
asserted, only ADSP is recognized.  
ADSC  
ZZ  
Input-  
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a  
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this  
pin has to be LOW or left floating. ZZ pin has an internal pull-down.  
I/O-  
Synchronous  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is  
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the  
memory location specified by the addresses presented during the previous clock rise of the  
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the  
pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state condition.  
DQs, DQPX  
VDD  
Power Supply Power supply inputs to the core of the device.  
VSS  
Ground  
Ground for the core of the device.  
Ground for the I/O circuitry.  
VSSQ  
VDDQ  
MODE  
I/O Ground  
I/O Power Supply Power supply for the I/O circuitry.  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD  
or left floating selects interleaved burst sequence. This is a strap pin and should remain  
static during device operation. Mode pin has an internal pull-up.  
TDO  
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the  
Synchronous  
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available  
on TQFP packages.  
Document #: 38-05540 Rev. *C  
Page 7 of 31  
1...45678910...31

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