Datasheet > 存储 > SRAM> ICY7C1362C-166BGI

ICY7C1362C-166BGI

更新时间： 2024-01-22 01:30:22

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	420K
描述
9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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ICY7C1362C-166BGI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	13 X 15 MM, 1.40 HEIGHT, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	最长访问时间：	3.5 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	9437184 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	220
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

ICY7C1362C-166BGI 数据手册

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CY7C1360C

CY7C1362C

PRELIMINARY

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 166 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36

and 524,288 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃^[2]), Burst Control inputs (ADSC, ADSP,

• 2.5V/3.3V I/O operation

• Fast clock-to-output times

ADV), Write Enables (BW , and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

and

— 2.8 ns (for 250-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the Byte Write control inputs. GW when active

• Asynchronous output enable

• Single Cycle Chip Deselect

• Offered in Lead-Free 100-pin TQFP, 119-ball BGA and

165-Ball fBGA packages

LOW cause

s all bytes to be written.

The CY7C1360C/CY7C1362C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Logic Block Diagram – CY7C1360C (256K x 36)

A0, A1, A

ADDRESS

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

CLR

LOGIC

ADSC

ADSP

BYTE

WRITE REGISTER

D ,DQPD

BYTE

WRITE DRIVER

D ,DQPD

DQ^{C ,}DQP

BYTE

WRITE DRIVER

DQ^{C ,}DQP

BYTE

WRITE REGISTER

OUTPUT

BUFFERS

OUTPUT

MEMORY

DQ s

SENSE

AMPS

ARRAY

REGISTERS

DQP

DQ^{B ,}DQP

BYTE

WRITE DRIVER

DQ^{B ,}DQP

BYTE

WRITE REGISTER

DQPD

BYTE

WRITE DRIVER

A ,DQPA

BYTE

WRITE REGISTER

BWE

INPUT

REGISTERS

ENABLE

PIPELINED

ENABLE

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05540 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised February 23, 2005

12 3 4 5 6 7...31

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与ICY7C1362C-166BGI相关器件

型号	品牌	描述	获取价格	数据表
ICY7C1362C-166BGXI	CYPRESS	9-Mbit (256K x 36/512K x 18) Pipelined SRAM	获取价格
ICY7C1362C-166BZI	CYPRESS	9-Mbit (256K x 36/512K x 18) Pipelined SRAM	获取价格
ICY7C1367B-166BGI	CYPRESS	9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM	获取价格
ICY7C1373C-100BGI	CYPRESS	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture	获取价格
ICY7C1373D-100BGI	CYPRESS	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture	获取价格
ICY7C1373D-100BGXI	CYPRESS	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture	获取价格

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