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ICS9DB803DGLFT PDF预览

ICS9DB803DGLFT

更新时间: 2024-02-11 04:50:18
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
22页 292K
描述
PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48

ICS9DB803DGLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP48,.3,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.24
系列:9DB输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:12.5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:48
实输出次数:8最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
Base Number Matches:1

ICS9DB803DGLFT 数据手册

 浏览型号ICS9DB803DGLFT的Datasheet PDF文件第16页浏览型号ICS9DB803DGLFT的Datasheet PDF文件第17页浏览型号ICS9DB803DGLFT的Datasheet PDF文件第18页浏览型号ICS9DB803DGLFT的Datasheet PDF文件第19页浏览型号ICS9DB803DGLFT的Datasheet PDF文件第20页浏览型号ICS9DB803DGLFT的Datasheet PDF文件第22页 
ICS9DB803D  
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2  
Revision History  
Rev.  
A
B
Issue Date  
8/15/2006  
Issuer  
Description  
Page #  
Updated electrical characteristics for final data sheet  
Added Input Clock Specs  
-
C
D
E
F
2/29/2008  
3/18/2008  
3/28/2008  
4/10/2008  
1/13/2009  
Updated Input Clock Specs  
Fixed typo in Input Clock Parameters  
Updated Electrical Char tables  
Updated Input Clock Specs  
G
Corrected part ordering information  
1. Clarified that Vih and Vil values were for Single ended inputs  
2. Added Differential Clock input parameters.  
3. Updated Electrical Characteristics to add propagation delay and  
phase noise information.  
4. Added SMBus electrical characteristics  
5. Added foot note about DIF input running in order for the SMBus  
interface to work  
6. Added foot note to Byte 1 about functionality of OE bits and OE  
pins.  
H
J
10/7/2009  
1/27/2011  
7. Updated/Reformatted General Description  
Updated Termination Figure 4  
Various  
12  
1. Update pin 2 pin-name and pin description from VDD to VDDR. This  
highlights that optimal peformance is obtained by treating VDDR as in  
analog pin. This is a document update only, there is no silicon change.  
Updated Vswing conditions to include "single-ended measurement"  
K
L
5/9/2011  
8/27/2012  
Various  
7
Updated Byte 2, bits 0~7 per char review. Outputs can be programmed  
with Byte 2 to be Stoppable or Free-Run with DIF_Stop pin, not the OE  
pins.  
M
N
9/18/2012  
7/10/2013  
14  
1
Typo discovered on front page "Output Features" section. Was: “50 –  
R. Wei  
MHz operation in PLL mode”; changed to: "50 –  
110  
MHz operation  
100  
in PLL mode”  
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2  
21  
ICS9DB803D  
REV N 071013  

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