Datasheet > ICS9E4101

ICS9E4101

更新时间： 2022-11-08 02:06:49

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	189K
描述
Programmable Timing Control HubTM for Intel Systems

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数据手册

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ICS9E4101 数据手册

DATASHEET

Programmable Timing Control Hub^TMfor Intel Systems ICS9E4101

Features/Benefits:

Recommended Application:

•

Supports tight ppm accuracy clocks for Serial-ATA and

PCI-Express

I-temp CK410 clock, Intel Yellow Cover part

•

Supports spread spectrum modulation, 0 to -0.5%

down spread

Output Features:

•

2 - 0.7V current-mode differential CPU pairs

6 - 0.7V current-mode differential SRC pair for SATA and

PCI-E

•

Supports CPU clks up to 400MHz

Uses external 14.318MHz crystal, external crystal load

caps are required for frequency tuning

•

1 - 0.7V current-mode differential CPU/SRC selectable

pair

•

Supports undriven differential CPU, SRC pair in PD#

for power management.

•

6 - PCI (33MHz)

3 - PCICLK_F, (33MHz) free-running

1 - USB, 48MHz

1 - DOT, 96MHz, 0.7V current differential pair

1 - REF, 14.318MHz

Pin Configuration

VDDPCI 1

GND 2

PCICLK3 3

PCICLK4 4

PCICLK5 5

56 PCICLK2

55 PCICLK1

54 PCICLK0

53 FS_C/TEST_SEL

52 REFOUT

51 GND

50 X1

49 X2

48 VDDREF

47 SDATA

46 SCLK

Key Specifications:

•

CPU outputs cycle-cycle jitter < 85ps

SRC output cycle-cycle jitter <125ps

PCI outputs cycle-cycle jitter < 500ps

+/- 300ppm frequency accuracy on CPU & SRC clocks

GND 6

VDDPCI 7

ITP_EN/PCICLK_F0 8

PCICLK_F1 9

PCICLK_F2 10

VDD48 11

Functionality

CPU

MHz

SRC

MHz

100.00

PCI

MHz

REF

MHz

14.318

USB

MHz

48.00

DOT

MHz

96.00

FS_C¹FS_B²FS_A²

USB_48MHz 12

GND 13

45 GND

44 CPUCLKT0

43 CPUCLKC0

42 VDDCPU

41 CPUCLKT1

40 CPUCLKC1

39 IREF

266.66

133.33

200.00

33.33

RESERVED

33.33

RESERVED

DOTT_96MHz 14

DOTC_96MHz 15

FS_B/TEST_MODE 16

Vtt_PwrGd#/PD 17

FS_A_410 18

100.00

14.318

48.00

96.00

SRCCLKT1 19

SRCCLKC1 20

VDDSRC 21

38 GNDA

37 VDDA

1. FS_C is a three-level input. Please see V_{IL_FS}and V_{IH_FS}specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FS_B and FS_A are low-threshold inputs. Please see the V_{IL_FS}and V_{IH_FS}

specifications in the Input/Supply/Common Output Parameters Table for correct values.

36 CPUCLKT2_ITP/SRCCLKT_7

35 CPUCLKC2_ITP/SRCCLKC_7

34 VDDSRC

33 SRCCLKT6

32 SRCCLKC6

31 SRCCLKT5

30 SRCCLKC5

29 GND

SRCCLKT2 22

SRCCLKC2 23

SRCCLKT3 24

SRCCLKC3 25

SRCCLKT4_SATA 26

SRCCLKC4_SATA 27

VDDSRC 28

56-pin SSOP

IDT^TMProgrammable Timing Control Hub^TMfor Intel Systems

1408A—01/25/10

12 3 4 5 6 7...19

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