Datasheet > ICS9DS400

ICS9DS400

更新时间： 2022-03-30 03:12:57

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	316K
描述
Four Output Differential Buffer for PCIe Gen 2 with Spread

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ICS9DS400 数据手册

Advance Information

ICS9DS400

Four Output Differential Buffer for PCIe Gen 2 with Spread

General Description

Features/Benefits

Bypass mode

The 9DS400 is pin compatible to the 9DB403, but adds the

ability to inject spread spectrum onto the incoming differential

clock, while maintaining good phase noise.

•

Supports undriven differential outputs in PD# and

SRC_STOP# modes for power management.

Recommended Application

DB400 where spread spectrum needs to be added to the

incoming clock.

Output Features

•

4 - 0.7V current-mode differential output pairs.

Supports Spread Injection mode and fanout mode.

Key Specifications

Two pin selectable down spread amounts: 0.5% and

0.25%.

•

Output cycle-cycle jitter < 50ps

•

50-110 MHz operation in PLL mode

50-400 MHz operation in Bypass mode

Output to Output skew <50ps

Phase jitter: PCIe Gen1 < 86ps peak to peak

Phase jitter: PCIe Gen2 < 3.0/3.1ps rms

Functional Block Diagram

OE(6,1)#

Spread

Generating

PLL

SRC_IN

SRC_IN#

STOP

LOGIC

DIF(6,5,2,1))

DIF_STOP

SPREAD_EN

CONTROL

LOGIC

BYPASS#_SSCG

IREF

SDATA

SCLK

Polarities shown assuming that OE_INV = 1

IDT^TM/ICS^TMFour Output Differential Buffer for PCIe Gen 2 with Spread

1626 09/17/09

12 3 4 5 6 7...19

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