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ICS95V157AGIT PDF预览

ICS95V157AGIT

更新时间: 2024-11-11 21:21:35
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 217K
描述
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, MO-153, TSSOP-48

ICS95V157AGIT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:0.240 INCH, MO-153, TSSOP-48针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.77系列:95V
输入调节:STANDARDJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:48实输出次数:10
最高工作温度:85 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.06 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL EXTENDED
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
最小 fmax:210 MHzBase Number Matches:1

ICS95V157AGIT 数据手册

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ICS95V157  
Integrated  
Circuit  
Systems, Inc.  
2.5V Single-Ended to SSTL_2 Clock Driver (45MHz - 233MHz)  
RecommendedApplication:  
Pin Configuration  
Single-ended clock input with zero delay board fan out  
ProductDescription/Features:  
Low skew, low jitter PLL clock driver  
1 to 10 differential clock distribution (SSTL_2)  
Feedback pin for input to output synchronization  
PD#forpowermanagement  
Spread Spectrum tolerant inputs  
SwitchingCharacteristics:  
CYCLE - CYCLE jitter: <60ps  
OUTPUT - OUTPUT skew: <60ps  
Period jitter:±30ps  
DUTY CYCLE: 49.5% - 50.5%  
Block Diagram  
48-Pin TSSOP  
6.10 mm. Body, 0.50 mm. pitch = TSSOP  
Functionality  
INPUTS  
OUTPUTS  
PLL State  
AVDD PD# CLK_INT CLKT CLKC FB_OUTT  
GND  
GND  
H
H
L
L
H
L
L
Bypassed/off  
Bypassed/off  
H
H
H
2.5V  
(nom)  
L
L
L
H
L
Z
Z
L
Z
Z
H
L
Z
Z
L
off  
off  
on  
on  
2.5V  
(nom)  
2.5V  
(nom)  
H
H
2.5V  
(nom)  
H
H
H
0501C—11/24/08  

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ICS95V157YG-T IDT

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PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, MO-15