Datasheet > ICS95V2F857AL-LF

ICS95V2F857AL-LF

更新时间： 2024-11-12 10:01:39

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
13页	146K
描述
Clock Driver, PDSO48

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中文翻译

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数据手册

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ICS95V2F857AL-LF 数据手册

ICS95V2F857A

Integrated

Circuit

Systems,Inc.

2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)

RecommendedApplication:

Pin Configuration

•

Heavy loaded/4 rank

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

•

DDR Memory Modules / Zero Delay Board Fan Out

Provides complete DDR registered DIMM solution

with ICSSSTVF16857, ICSSSTVF16859 or

ICSSSTVA32852

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

ProductDescription/Features:

CLKC2

CLKT2

VDD

CLKC7

CLKT7

VDD

•

Higher drive than the 95V857 series devices

Low skew, low jitter PLL clock driver

1 to 10 differential clock distribution (SSTL_2)

VDD

PD#

CLK_INT

CLK_INC

VDD

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

FB_INT

FB_INC

VDD

FB_OUTC

FB_OUTT

GND

CLKC8

CLKT8

VDD

CLKT9

CLKC9

GND

•

Feedback pins for input to output synchronization

PD#forpowermanagement

•

SpreadSpectrum-tolerantinputs

Auto PD when input signal removed

Specifications:

•

Meets PC3200 Class A+ specification for DDR-I 400

support

48-Pin TSSOP/TVSOP

6.10 mm Body, 0.50 mm Pitch = TSSOP

4.40 mm Body, 0.40 mm Pitch = TVSOP

•

Covers all DDRI speed grades

SwitchingCharacteristics:

•

CYCLE - CYCLE jitter: <50ps

OUTPUT - OUTPUT skew: <40ps

Period jitter: 30ps

Block Diagram

Functionality

FB_OUTT

FB_OUTC

INPUTS

OUTPUTS

PLL State

CLKT0

CLKC0

AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC

GND

Bypassed/off

CLKT1

CLKC1

Control

CLKT2

CLKC2

2.5V

(nom)

off

PD#

Logic

2.5V

(nom)

CLKT3

CLKC3

2.5V

(nom)

CLKT4

CLKC4

2.5V

(nom)

FB_INT

FB_INC

CLKT5

CLKC5

2.5V

(nom)

<20MHz)⁽¹⁾

PLL

CLK_INC

CLKT6

CLKC6

CLK_INT

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

1065A—02/03/05

12 3 4 5 6 7...13

中文翻译

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